Wafer container with staggered wall structure

Abstract

A wafer container comprising a base and a cover that nest together. The base includes a staggered wall structure composed of inner and outer walls. The staggered wall structure is arranged so that forces from side impacts are absorbed principally by outer wall segments. A rib on the cover restrains the outer wall segments from flexing beyond the inner wall diameter. Reference tabs on the base facilitate alignment of the base to the cover.

1 - 22 . (canceled) 
     
     
         23 . A wafer container for storing a plurality of semiconductor wafers, the wafer container comprising:
 a cover;   a base comprising an upper surface and further comprising a latch on at least two corners of the base;   a notch on the cover comprising a first edge and a second edge, wherein the second edge is longer than the first edge, and wherein the second edge comprises a ramp for receiving the latch;   a wall structure extending from the base, wherein the wall structure comprises inner wall segments that alternate with outer wall segments;   a pair of reference tabs located on each side of the upper surface of the base; and   a plurality of brackets on the cover, wherein each bracket comprises a pair of recesses that slip over a respective pair of the reference tabs to form a closed wafer container.   
     
     
         24 . The wafer container of  claim 23 , further comprising a plurality of semiconductor wafers stored therein. 
     
     
         25 . A wafer container comprising:
 a base comprising a plurality of inner walls having a first arc and a plurality of outer walls having a second arc, wherein the outer walls occupy a different radial axis than the inner walls;   a plurality of angular sectors, each angular sector having a boundary defined by either the first or the second arc;   the walls formed of individual wall segments such that each inner wall segment is unconnected to the outer wall segments, each inner wall segment alternating with an outer wall segment, and sharing between 0.1 to 25% of a common angular sector with an outer wall segment, wherein the inner wall segments are capable of moving independently from the outer wall segments when the wafer container receives an external impact; and   a cover comprising a plurality of brackets that include a pair of recesses, wherein the recesses of each bracket slip over a respective pair of reference tabs to form a closed wafer container.   
     
     
         26 . The wafer container of  claim 25 , further comprising a plurality of semiconductor wafers stored therein. 
     
     
         27 . The wafer container of  claim 25 , further comprising:
 a pair of reference tabs on opposite sides of an upper surface of the base.   
     
     
         28 . A wafer container comprising:
 a base comprising a major surface that includes a plurality of angular sectors;   segmented inner walls formed of individual wall segments located on a respective first arc on the base and separated from an adjacent wall by a space in a radial direction along the major surface;   segmented outer walls formed of individual wall segments located on a respective second arc on the base and separated from an adjacent wall by a space in a radial direction along the major surface, each of the outer walls being unconnected to the inner walls along the entire length of the inner walls, wherein between 0.1 and 25% of the arc length of the first arc is located in the same angular sectors as the arc length of the second arc; and   a slot in at least one of the outer walls that extends at least substantially along the entire height of the outer walls, and has a width dimension that is greater than the distance between an inner wall and an outer wall.   
     
     
         29 . The wafer container of  claim 28 , further comprising a plurality of semiconductor wafers stored therein. 
     
     
         30 . The wafer container of  claim 28 , wherein the segmented inner walls alternate with the segmented outer walls. 
     
     
         31 . The wafer container of  claim 28 , further comprising:
 a cover that engages to the base to form a closed container;   a plurality of brackets on the cover, wherein each bracket includes a pair of recesses; and   a pair of reference tabs on opposite sides of an upper surface of the base;   wherein the recesses of each bracket slip over a respective pair of reference tabs to form a closed wafer container.   
     
     
         32 . The wafer container of  claim 28 , further comprising:
 a cover that engages to the base to form a closed container.   
     
     
         33 . The wafer container of  claim 32 , wherein the cover comprises a notch comprising a ramp, wherein the ramp comprises a positive slope relative to a top surface of the cover for receiving the base. 
     
     
         34 . The container of  claim 32 , further comprising:
 a pair of latches connected to the base, wherein the latches secure the base to the cover when each latch locks onto a respective ramp on the cover.   
     
     
         35 . A wafer container for storing a plurality of semiconductor wafers, the wafer container comprising:
 a cover;   a base having a circumference that includes a plurality of angular sectors;   segmented inner walls formed of individual wall segments located on a respective first arc on the base and separated from an adjacent wall by a space in a radial direction along the circumference; and   segmented outer walls formed of individual wall segments located on a respective second arc on the base and separated from an adjacent wall by a space in a radial direction along the circumference, each of the walls being unconnected to the other walls, wherein between 0.1 and 50% of the arc length of the first arc is located in the same angular sectors as the arc length of the second arc, and wherein the segmented inner walls alternate with the segmented outer walls.   
     
     
         36 . The wafer container of  claim 35 , further comprising a plurality of semiconductor wafers stored therein. 
     
     
         37 . The wafer container of  claim 35 , wherein between 0.1 to 25% of the arc length of the first arc is located in the same angular sector as the arc length of the second arc. 
     
     
         38 . The wafer container of  claim 35 , wherein a slot is provided in at least one of the outer walls, the slot defined by a lower portion that extends near the level of the base, and by a lateral portion that extends to the upper surface of the outer wall. 
     
     
         39 . The wafer container of  claim 35 , further comprising:
 a plurality of brackets on the cover, wherein each bracket includes a pair of recesses; and   a pair of reference tabs on opposite sides of an upper surface of the base.   
     
     
         40 . The wafer container of  claim 35 , further comprising:
 a plurality of brackets on the cover, wherein each bracket includes a pair of recesses; and   a pair of reference tabs on opposite sides of an upper surface of the base;   wherein the recesses of each bracket slip over a respective pair of reference tabs to form a closed wafer container.   
     
     
         41 . The wafer container of  claim 35 , wherein the a notch is located on a top surface of the cover, and wherein the notch includes a ramp that has a positive slope relative to the top surface of the cover. 
     
     
         42 . The container of  claim 35 , wherein the a notch is located on a top surface of the cover, and wherein the notch includes a ramp that has a positive slope relative to the top surface of the cover, and further comprising a pair of latches connected to the base, wherein the latches secure the base to the cover when each latch locks onto a respective ramp on the cover.