Circuit and method for correcting skew in a plurality of communication channels for communicating with a memory device, memory controller, system and method using the same, and memory test system and method using the same

Abstract

In a circuit, memory controller, memory system, and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences.

1 . A circuit for correcting skew among a plurality of communication channels used in communicating with a memory circuit, comprising:
 a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels;   a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels;   a detection circuit for receiving the reflected signals and detecting relative signal propagation time differences between the plurality of channels; and   a delay circuit coupled to at least one of the channels for setting a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences.   
     
     
         2 . The circuit of  claim 1 , further comprising a plurality of delay circuits coupled to a plurality of the channels for setting a plurality of signal propagation delays in the plurality of channels based on the detected relative signal propagation time differences. 
     
     
         3 . The circuit of  claim 1 , wherein the reference signal is a step signal. 
     
     
         4 . The circuit of  claim 1 , wherein the circuit is at least one of a built-off-test (BOT) circuit used in sending test signals to the memory circuit and a memory controller circuit for controlling the memory circuit. 
     
     
         5 . The circuit of  claim 1 , wherein the memory circuit is at least one of a device under test (DUT), a DRAM memory circuit, and a DDR 3  DRAM memory circuit. 
     
     
         6 . The circuit of  claim 1 , wherein one of the plurality of channels is a channel for communicating a DQS data strobe signal. 
     
     
         7 . The circuit of  claim 6 , wherein the delay circuit is set such that a phase shift of 90 degrees is introduced in the channel for communicating the DQS data strobe signal. 
     
     
         8 . The circuit of  claim 1 , wherein the delay circuit is at least one of a delay line, a programmable delay line, and an asynchronous programmable delay line. 
     
     
         9 . The circuit of  claim 1 , wherein the transmitting circuit comprises a source termination circuit for terminating the input ends of the channels. 
     
     
         10 . The circuit of  claim 9 , wherein the output ends of the channels are configured as open circuits when the signals are transmitted through the channels. 
     
     
         11 . The circuit of  claim 10 , wherein the output ends of the channels are disconnected from the memory circuit when the signals are transmitted through the channels. 
     
     
         12 . A memory controller for controlling a memory circuit, the memory controller having a de-skewing capability for correcting skew among a plurality of communication channels used in communicating with the memory circuit, the memory controller comprising:
 a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels;   a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels;   a detection circuit for receiving the reflected signals and detecting relative signal propagation time differences between the plurality of channels; and   a delay circuit coupled to at least one of the channels for setting a signal propagation delay in the at least one of the channels based on the detected signal propagation time differences.   
     
     
         13 . The memory controller of  claim 12 , further comprising a plurality of delay circuits coupled to a plurality of the channels for setting a plurality of signal propagation delays in the plurality of channels based on the detected signal propagation time differences. 
     
     
         14 . The memory controller of  claim 12 , wherein the reference signal is a step signal. 
     
     
         15 . The memory controller of  claim 12 , wherein the memory circuit is at least one of a DRAM memory circuit and a DDR 3  DRAM memory circuit. 
     
     
         16 . The memory controller of  claim 12 , wherein one of the plurality of channels is a channel for communicating a DQS data strobe signal. 
     
     
         17 . The memory controller of  claim 16 , wherein the delay circuit is set such that a phase shift of 90 degrees is introduced in the channel for communicating the DQS data strobe signal. 
     
     
         18 . The memory controller of  claim 12 , wherein the transmitting circuit comprises a source termination circuit for terminating the input ends of the channels. 
     
     
         19 . A method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, comprising:
 transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels;   receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels;   detecting relative signal propagation time differences between the plurality of channels; and   setting a signal propagation delay in at least one of the channels based on the detected relative signal propagation time differences.   
     
     
         20 . The method of  claim 19 , further comprising setting a plurality of signal propagation delays in the plurality of channels based on the detected relative signal propagation time differences.