Apparatus and method for controlling the access operation by a plurality of data processing devices to a memory

Abstract

In an apparatus for controlling the access operation by a plurality of data processing devices to a memory, each data processing device is assigned a respective address region which indicates the part of the addresses of the memory which the respective data processing device can access. A control device blocks an access operation by a data processing device to the memory if the access operation address is not located in the address region which is assigned to the respective data processing device.

1 . A method for controlling the access operation by a plurality of data processing devices to a memory, comprising:
 storing address regions, each data processing device being assigned at least one respective address region which indicates a portion of the memory which the respective data processing device may access; and   comparing access operations of the data processing devices to the memory with the stored address regions, and blocking an access operation of a data processing device to the memory if an address of an access operation of a respective data processing device is not located in the at least one address region.   
     
     
         2 . An system, comprising:
 a plurality of data processing devices;   a memory access unit coupled to said data processing devices and memory comprising a plurality of registers for storing address regions, each data processing device being assigned at least one respective address region which indicates the part of the memory which the respective data processing device may access; and   control devices for comparing addresses of access operations of the data processing devices to the memory with the stored address regions, and for blocking an access operation of a data processing device to the memory if the address of an access operation of a respective data processing device is not located in the at least one address region which is assigned to the respective data processing device.   
     
     
         3 . The system according to  claim 2 , wherein a specific data processing device of the data processing devices is connected to the registers in order to store the address regions in the memory devices. 
     
     
         4 . The system according to  claim 2 , wherein the address regions are stored in the registers during the initialization of the apparatus. 
     
     
         5 . The system according to  claim 2 , wherein the apparatus also has a signalling device for sensing and signalling a blocked access operation, the signalling device being connected to the control devices in order to sense the blocked access operation, and is connected to the specific data processing device in order to signal the blocked access operation to the specific data processing device. 
     
     
         6 . The system according to  claim 5 , wherein the signalling device has a memory device for storing information relating to blocked access operations. 
     
     
         7 . The system according to  claim 6 , wherein information relating to a blocked access operation has the blocked address, the blocked data and connection information. 
     
     
         8 . The system according to  claim 2 , wherein the data processing devices have processors, digital signal processors, microcontrollers and/or direct memory access controllers. 
     
     
         9 . The system according to  claim 2 , wherein the data processing devices are connected to the apparatus via buses. 
     
     
         10 . An apparatus for controlling access operation by a plurality of data processing devices to a memory, comprising:
 memory devices for storing address regions, each data processing device being assigned at least one respective address region which indicates a portion of the memory which the respective data processing device may access; and   control devices for comparing access operations of the data processing devices to the memory with the stored address regions, and for blocking an access operation of a data processing device to the memory if an address of an access operation of a respective data processing device is not located in at least one address region which is assigned to the respective data processing device.   
     
     
         11 . The apparatus according to  claim 10 , wherein a specific data processing device of the data processing devices is connected to the memory devices in order to store the address regions in the memory devices. 
     
     
         12 . The apparatus according to  claim 10 , wherein the address regions are stored in the memory devices during the initialization of the apparatus. 
     
     
         13 . The apparatus according to  claim 10 , wherein the apparatus also has a signalling device for sensing and signalling a blocked access operation, the signalling device being connected to the control devices in order to sense the blocked access operation, and is connected to the specific data processing device in order to signal the blocked access operation to the specific data processing device. 
     
     
         14 . The apparatus according to  claim 13 , wherein the signalling device has a memory device for storing information relating to blocked access operations. 
     
     
         15 . The apparatus according to  claim 14 , wherein information relating to a blocked access operation has the blocked address, the blocked data and connection information. 
     
     
         16 . The apparatus according to  claim 10 , wherein the data processing devices have processors, digital signal processors, microcontrollers and/or direct memory access controllers. 
     
     
         17 . The apparatus according to  claim 10 , wherein the data processing devices are connected to the apparatus via buses. 
     
     
         18 . The apparatus according to  claim 17 , wherein the buses have Advanced Microprocessor Bus Architecture buses, Advanced High-speed Bus buses and/or Flexible Peripheral Interconnect buses. 
     
     
         19 . The apparatus according to  claim 10 , wherein the memory has a random access memory or a dynamic random access memory. 
     
     
         20 . The apparatus according to  claim 10 , wherein the memory devices have registers, in each case one register being assigned to one data processing device.