US2012159054A1PendingUtilityA1

Flash memory device with multi-level cells and method of writing data therein

Assignee: CHEON WON-MOONPriority: Oct 30, 2006Filed: Feb 28, 2012Published: Jun 21, 2012
Est. expiryOct 30, 2026(~0.3 yrs left)· nominal 20-yr term from priority
G06F 3/064G11C 16/04G11C 16/16G06F 2212/2022G06F 3/0613G06F 2212/7208G06F 12/0246G06F 3/0679G06F 2212/1021G11C 2211/5641G06F 3/0631G11C 16/02G06F 3/0632G06F 2212/7202
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Claims

Abstract

In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.

Claims

exact text as granted — not AI-modified
1 . A method of writing data in a flash memory system, the flash memory system forming an address mapping pattern in accordance with a log block mapping scheme, the method comprising:
 allocating a first block and a second block to a log block;   writing data into the first block; and   copying valid pages of the first block into the second block.   
     
     
         2 . The method as set forth in  claim 1 , wherein the first and second blocks are single-level cell (SLC) blocks. 
     
     
         3 . The method as set forth in  claim 1 , wherein the first and second blocks are multi-level cell (MLC) blocks in which fast pages are allocated to available storage fields. 
     
     
         4 . The method as set forth in  claim 1 , further comprising:
 determining a size of valid pages of the first block for copying the valid pages into the second block.   
     
     
         5 . The method as set forth in  claim 4 , further comprising:
 copying the valid pages into data block when the size of valid pages corresponds to a full size of the second block.   
     
     
         6 . The method as set forth in  claim 5 , wherein the full size of the second block corresponds to a number of single-level cell (SLC) pages of the second block. 
     
     
         7 . The method as set forth in  claim 2 , wherein after data of the valid pages of the first block are copied into the second block, the first block is erased. 
     
     
         8 . The method as set forth in  claim 2 , further comprising:
 writing data into the second block; and   determining a size of valid pages of the second block for copying the valid pages of the second block into the first block or a data block.   
     
     
         9 . The method as set forth in  claim 8 , wherein after data of the valid pages of the second block are copied into the first block, the second block is erased. 
     
     
         10 . A memory system which forms an address mapping pattern on accordance with a log block mapping scheme, comprising:
 a flash memory device including pluralities of single-level cell (SLC) and multi-level cell (MLC) blocks as storage fields; and   a controller configured to control the flash memory device and to allocate a first block and a second block to a log block for writing an externally supplied data,   wherein the controller controls the flash memory device to exchange valid pages between the first block and the second block during a write operation of the externally supplied data until a size of the valid pages reaches a predetermined value.   
     
     
         11 . The memory system of  claim 10 , wherein the first and second blocks are SLC blocks. 
     
     
         12 . The memory system of  claim 10 , wherein the predetermined value corresponds to full size of the SLC block. 
     
     
         13 . The memory system of  claim 10 , wherein the first and second blocks are MLC blocks in which fast pages are allocated to available storage fields. 
     
     
         14 . The memory system of  claim 13 , wherein the predetermined value corresponds to a size of SLC pages in a single MLC block. 
     
     
         15 . The memory system of  claim 10 , wherein the controller controls the flash memory device to copy the valid pages into a data block when the size of the valid pages reach a predetermined value. 
     
     
         16 . The memory system of  claim 10 , wherein the externally supplied data is correspondent to a overwriting pattern. 
     
     
         17 . The memory system of  claim 10 , wherein the controller controls the flash memory device to erase the first block after the valid pages of the first block are copied into the second block.

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