System Management Mode Inter-Processor Interrupt Redirection

Abstract

A method, processor, and system are disclosed. In one embodiment method includes a first processor core among several processor cores entering into a system management mode. At least one of the other additional processor cores apart from the first processor core remain operational and do not enter the system management mode. Then, once in the system management mode, the first processor core responds to an inter-processor interrupt.

1 . A processor comprising:
 a first core to enter into a system management mode and including redirection logic to handle receipt and redirection of an inter-processor interrupt while in the system management mode.   
     
     
         2 . The processor of  claim 1 , wherein the first core is further operable to save an interrupt descriptor table in a memory to allow processing of interrupts while in the system management mode, store a pointer to the interrupt descriptor table in an interrupt descriptor table register (IDTR) of the first core, and enable inter-processor interrupts. 
     
     
         3 . The processor of  claim 2 , wherein the first core is further to:
 after having received an inter-processor interrupt, save a current system context into the memory;   set up a new super-jump system context to be used upon a super-jump;   perform the super-jump to an operating system inter-processor interrupt handler location; and   execute the operating system inter-processor interrupt handler.   
     
     
         4 . The processor of  claim 3 , wherein the first core is further to:
 after having executed the operating system inter-processor interrupt handler, return to the pre-super-jump location;   restore the current system context from the memory; and   exit from the system management mode.   
     
     
         5 . The processor of  claim 3 , wherein the first core is further operable to securely measure an operating system that controls the operating system inter-processor interrupt handler with a system management interrupt transfer monitor prior to allowing the operating system to gain control and execute the handler, and upon the measurement, transfer control to the operating system. 
     
     
         6 . The processor of  claim 3 , wherein the first core is further operable to:
 set a bit in a machine specific register of the first core in response to the inter-processor interrupt to include one or more first core control registers and a first core global descriptor table register in a context switch associated with the super-jump.   
     
     
         7 . The processor of  claim 1 , further comprising one or more cores of the processor to remain operational and not enter the system management mode. 
     
     
         8 . A method comprising:
 receiving a first broadcast system management interrupt in a plurality of cores of a multicore processor;   entering into the system management mode of the plurality of cores responsive to the first broadcast system management interrupt;   receiving a second broadcast system management interrupt in the plurality of cores; and   exiting the system management mode of at least a first core of the plurality of cores responsive to determining that the at least first core is idle in the system management mode.   
     
     
         9 . The method of  claim 8 , further comprising:
 after the first core has entered the system management mode, saving an interrupt descriptor table to allow processing of interrupts by the first core; and   enabling inter-processor interrupts to the first core.   
     
     
         10 . The method of  claim 9 , further comprising:
 after the first core has received an inter-processor interrupt,   saving a current system context for the first core into a memory;   setting up a new super-jump system context for the first core to be used upon a super-jump;   performing a super-jump to an operating system inter-processor interrupt handler location; and   executing the operating system inter-processor interrupt handler.   
     
     
         11 . The method of  claim 10 , further comprising:
 after the execution of the operating system inter-processor interrupt handler,   returning to the pre-super-jump location;   restoring the current system context for the first core from the memory; and   exiting the first core from the system management mode.   
     
     
         12 . The method of  claim 10 , further comprising:
 securely measuring an operating system that controls the operating system inter-processor interrupt handler with a system management interrupt transfer monitor prior to allowing the operating system to gain control and execute the handler; and   upon the measurement, the system management interrupt transfer monitor transferring control to the operating system.   
     
     
         13 . The method of  claim 12 , further comprising setting up a virtual machine control structure. 
     
     
         14 . The method of  claim 13 , further comprising receiving a virtual machine exit command responsive to the first broadcast system management interrupt and setting up a secure environment to launch the operating system inter-processor interrupt handler. 
     
     
         15 . The method of  claim 10 , further comprising:
 setting a bit in a machine specific register of the first core in response to the inter-processor interrupt to include one or more control registers and a global descriptor table register in a context switch associated with the super-jump.   
     
     
         16 . The method of  claim 8 , further comprising:
 receiving a first targeted system management interrupt in the first core;   entering into the system management mode of the first core responsive to the first targeted system management interrupt; and   not entering into the system management mode of at least one other core of the plurality of cores responsive to the first targeted system management interrupt.   
     
     
         17 . An article comprising a machine-accessible storage medium including instructions that when executed cause a system to:
 receive a first broadcast system management interrupt in a plurality of cores of a multicore processor;   enter into the system management mode of the plurality of cores responsive to the first broadcast system management interrupt;   receive a second broadcast system management interrupt in the plurality of cores; and   exit the system management mode of at least a first core of the plurality of cores responsive to determining that the at least first core is idle in the system management mode.   
     
     
         18 . The article of  claim 17 , further comprising instructions that when executed enable the system to:
 after the first core has entered the system management mode, save an interrupt descriptor table to allow processing of interrupts by the first core; and   enable inter-processor interrupts to the first core.   
     
     
         19 . The article of  claim 18 , further comprising instructions that when executed enable the system to:
 after the first core has received an inter-processor interrupt, save a current system context for the first core into a memory;   set up a new super-jump system context for the first core to be used upon a super-jump;   perform a super-jump to an operating system inter-processor interrupt handler location; and   execute the operating system inter-processor interrupt handler.   
     
     
         20 . The article of  claim 19 , further comprising instructions that when executed enable the system to:
 after the execution of the operating system inter-processor interrupt handler, return to the pre-super-jump location;   restore the current system context for the first core from the memory; and   exit the first core from the system management mode.