Semiconductor memory and manufacturing method

Abstract

A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.

1 . A semiconductor memory comprising:
 a memory cell array that includes data cells of x bits and redundant cells of y bits for each word;   a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and   a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.   
     
     
         2 . The semiconductor memory according to  claim 1 , further comprising a conversion circuit that converts, if the defective-cell position data for the specified word stored in the position-data storage unit are data indicating what number bits are the defective cells in the specified word, the data into a bit string of x+y bits indicating whether cells of the specified word are defective, wherein
 the read circuit reads the data from cells of x bits based on the bit string of x+y bits for the specified word converted by the conversion circuit, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.   
     
     
         3 . The semiconductor memory according to  claim 2 , wherein the read circuit and the conversion circuit are combined into a single circuit by logic synthesis. 
     
     
         4 . The semiconductor memory according to  claim 1 , further comprising a conversion circuit that converts, if the defective-cell position data for the specified word stored in the position-data storage unit are a combination number indicating a combination of bit positions of the defective cells, the combination number into a bit string of x+y bits indicating whether cells of the specified word are defective, wherein
 the read circuit reads the data from cells of x bits based on the bit string of x+y bits for the specified word converted by the conversion circuit, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.   
     
     
         5 . The semiconductor memory according to  claim 4 , wherein the read circuit and the conversion circuit are combined into a single circuit by logic synthesis. 
     
     
         6 . A semiconductor memory comprising:
 a memory cell array that includes data cells of x bits and redundant cells of y bits for each word;   a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and   a write circuit that writes, based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as write address, write data of x bits for the specified word into the data cells of x bits and the redundant cells of y bits of the specified word.   
     
     
         7 . The semiconductor memory according to  claim 6 , further comprising a conversion circuit that converts, if the defective-cell position data for the specified word stored in the position-data storage unit are data indicating what number bits are the defective cells in the specified word, the data into a bit string of x+y bits indicating whether cells of the specified word are defective, wherein
 the write circuit writes the write data of x bits for the specified word into the data cells of x bits and the redundant cells of y bits of the specified word based on the bit string of x+y bits for the specified word converted by the conversion circuit.   
     
     
         8 . The semiconductor memory according to  claim 7 , wherein the write circuit and the conversion circuit are combined into a single circuit by logic synthesis. 
     
     
         9 . The semiconductor memory according to  claim 6 , further comprising a conversion circuit that converts, if the defective-cell position data for the specified word stored in the position-data storage unit are a combination number indicating a combination of bit positions of the defective cells, the combination number into a bit string of x+y bits indicating whether cells of the specified word are defective, wherein
 the write circuit writes the write data of x bits for the specified word into the data cells of x bits and the redundant cells of y bits of the specified word based on the bit string of x+y bits for the specified word converted by the conversion circuit.   
     
     
         10 . The semiconductor memory according to  claim 9 , wherein the write circuit and the conversion circuit are combined into a single circuit by logic synthesis. 
     
     
         11 . A manufacturing method comprising:
 testing a memory cell array that is included in a semiconductor memory and includes data cells of x bits and redundant cells of y bits for each word, the semiconductor memory including the memory cell array, a position-data storage unit, and a function of compensating redundant cells of up to y bits for each word; and   writing position data of defective cells of the data cells and the redundant cells of each word obtained from the testing into the position-data storage unit by electron-beam printing.