Pin attachment

Abstract

A microelectronic package includes a substrate having a first region, a second region, a first surface, and a second surface remote from the first surface. At least one microelectronic element overlies the first region on the first surface. First electrically conductive elements are exposed at one of the first surface and the second surface of the substrate within the second region with at least some of the first conductive elements electrically connected to the at least one microelectronic element. Substantially rigid metal elements overlie the first conductive elements and have end surfaces remote therefrom. A bond metal joins the metal elements with the first conductive elements, and a molded dielectric layer overlies at least the second region of the substrate and has a surface remote from the substrate. The end surfaces of the metal elements are at least partially exposed at the surface of the molded dielectric layer.

1 . A microelectronic package comprising:
 a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;   at least one microelectronic element overlying the first region on the first surface;   first electrically conductive elements exposed at one of the first surface and the second surface of the substrate within the second region, at least some of the first conductive elements electrically connected to the at least one microelectronic element;   substantially rigid metal elements overlying the first conductive elements and having end surfaces remote therefrom;   a bond metal joining the metal elements with the first conductive elements; and   a molded dielectric layer overlying at least the second region of the substrate and having a surface remote from the substrate, wherein the end surfaces of the metal elements are at least partially exposed at the surface of the molded dielectric layer.   
     
     
         2 . The microelectronic package of  claim 1 , wherein at least some of the first conductive elements are exposed at the second surface of the substrate within the second region and the molded dielectric layer overlies at least the second surface. 
     
     
         3 . The microelectronic package of  claim 1 , wherein the first conductive elements are exposed at the first surface of the substrate within the second region and the molded dielectric layer overlies at least the first surface. 
     
     
         4 . The microelectronic package of  claim 3 , further including second conductive elements exposed at the second surface of the substrate and electrically connected with at least some of the first conductive elements. 
     
     
         5 . The microelectronic package of  claim 1 , wherein a first one of the metal elements is adapted for carrying a first signal electric potential and a second one of the metal elements is adapted for simultaneously carrying a second electric potential, said second electric potential being different from said first signal electric potential. 
     
     
         6 . The microelectronic package of  claim 1 , wherein the molded dielectric layer overlies said microelectronic element. 
     
     
         7 . The microelectronic package of  claim 1 , wherein the molded dielectric layer has a first height above the first region and a second height above the second region, the first height being different from the second height. 
     
     
         8 . The microelectronic package of  claim 7 , wherein the first height is greater than the second height. 
     
     
         9 . The microelectronic package of  claim 1 , wherein the end surfaces of the metal elements are coplanar with the surface of the molded dielectric layer. 
     
     
         10 . The microelectronic package of  claim 9 , further including conductive pads exposed at the surface of the molded dielectric layer and electrically connected with the metal elements. 
     
     
         11 . The microelectronic package of  claim 1 , wherein the end surfaces of the metal elements are positioned between the first surface of the substrate and the surface of the molded dielectric layer, and wherein the molded dielectric layer has holes formed therein extending from the outside surface to expose the end surfaces of the metal elements. 
     
     
         12 . The microelectronic package of  claim 1 , wherein the molded dielectric layer has a major surface overlying at least the second region of the substrate, and the end surfaces of the metal elements project above the major surface. 
     
     
         13 . The microelectronic package of  claim 1 , wherein the metal elements taper from greater widths at the end surfaces in a direction towards the first conductive elements. 
     
     
         14 . The microelectronic package of  claim 13 , wherein the metal elements have surfaces of revolution about an axis. 
     
     
         15 . The microelectronic package of  claim 1 , wherein the metal elements are cylindrical in shape. 
     
     
         16 . The microelectronic package of  claim 1 , wherein the metal elements include a base region adjacent the bond metal and a tip region, adjacent to the end, and wherein each of the rigid metal elements has an axis and a circumferential surface which slopes toward or away from the axis in the vertical direction along the axis, such that the slope of the circumferential wall changes abruptly at a boundary between the tip region and the base region. 
     
     
         17 . The microelectronic package of  claim 1 , wherein the metal elements consist essentially of a material selected from the group consisting of copper, nickel, gold, and any combination thereof. 
     
     
         18 . The microelectronic package of  claim 17 , wherein the bond metal has a melting temperature below 300° C. 
     
     
         19 . The microelectronic package of  claim 1 , wherein a height of the metal elements extend through at least 60% of the thickness of the molded dielectric layer overlying at least the second region of the substrate. 
     
     
         20 . The microelectronic package of  claim 1 , wherein a height of the bond metal extends through at least 60% of the thickness of the molded dielectric layer overlying at least the second region of the substrate. 
     
     
         21 . The microelectronic package of  claim 20 , wherein the metal elements are pads. 
     
     
         22 . The microelectronic package of  claim 1 , further including a second substrate disposed on the outside surface of the molded dielectric layer and second conductive pads exposed at a surface of the second substrate and electrically connected to the end surfaces of the metal elements. 
     
     
         23 . A microelectronic assembly, comprising:
 a first microelectronic package according to  claim 1 ; and   a second microelectronic package including an outer surface having a plurality of connection elements exposed at a surface thereof and a microelectronic element electrically connected to the connection elements;   wherein at least a portion of the outer surface of the second microelectronic package overlies at least a portion of the surface of the molded dielectric layer and the connection elements of the second microelectronic package are electrically and mechanically connected to the end surfaces of the conductive projections of the first microelectronic package.   
     
     
         24 . A microelectronic package comprising:
 a substrate having a first surface and a second surface remote from the first surface;   a microelectronic element overlying the second surface;   first electrically conductive pads exposed at the first surface of the substrate within the second region, at least some of the first conductive pads electrically connected to the microelectronic element; and   substantially rigid metal elements overlying the first conductive elements and having end surfaces remote therefrom;   a bond metal joining the metal elements with the first conductive elements; and   a dielectric encapsulant layer overlying at least the second regions of the first surface, wherein the first and second conductive projections have end surfaces remote from the second region and are at least partially exposed at a surface of the dielectric encapsulant layer.   
     
     
         25 . A method for making a microelectronic package, comprising:
 providing a microelectronic assembly including a first substrate having a first surface with a plurality of electrically conductive elements exposed thereon, a carrier having a second surface spaced apart from the first surface of the substrate, and a plurality of substantially rigid metal elements extending from the carrier and joined to the conductive elements; and   removing the carrier from the microelectronic assembly, thereby exposing contact surfaces of respective ones of the plurality of metal elements remote from the first conductive pads.   
     
     
         26 . The method of  claim 25 , further comprising, prior to the step of removing the carrier, injecting a dielectric material between the first and second surfaces and around the conductive projections to form a molded dielectric layer. 
     
     
         27 . The method of  claim 25 , wherein each of the plurality of metal elements are joined to respective ones of the conductive elements through a bond metal. 
     
     
         28 . The method of  claim 25 , wherein the step of removing the carrier includes at least one of etching, lapping or peeling the carrier. 
     
     
         29 . The method of  claim 25 , further including forming the microelectronic subassembly from a first subassembly including the first substrate and the conductive elements and a second subassembly including the carrier and the metal elements, wherein the metal elements exposed first surfaces remote from the second surface, and wherein the microelectronic assembly is formed by attaching the first surfaces of the metal elements to the conductive elements of the second subassembly. 
     
     
         30 . The method of  claim 29 , wherein the step of forming the first microelectronic assembly includes attaching at least the first surfaces of the metal elements to the conductive pads of the second assembly by forming a plurality of masses of a bonding metal that are affixed to the first surfaces of the conductive projections and to respective ones of the conductive elements such that at least a portion of the bonding metal is disposed between the first surfaces and the conductive elements. 
     
     
         31 . The method of  claim 30 , wherein the bonding metal masses are formed by depositing solder on one of the group consisting of the conductive projections and the conductive elements. 
     
     
         32 . The method of  claim 25 , wherein the microelectronic assembly further includes a microelectronic element affixed on the substrate and electronically connected to at least some of the conductive elements. 
     
     
         33 . The method of  claim 32 , wherein the microelectronic element is included in the microelectronic assembly by a step of affixing the microelectronic element on the first substrate carried out prior to the step of removing the carrier. 
     
     
         34 . The method of  claim 32 , wherein the first surface of the first substrate includes first and second regions, the conductive elements being exposed at the first surface within the first region and the microelectronic element being attached on the first surface within the second region, the method further including molding a dielectric layer over the first and second regions of the first surface and at least a portion of said microelectronic element, wherein the molded dielectric layer includes an outer surface, and wherein the contact surfaces of the metal elements are exposed at the outer surface of the molded dielectric layer. 
     
     
         35 . The method of  claim 25 , further comprising affixing a microelectronic element to the first substrate and electronically connecting the microelectronic element to at least some of the conductive elements after the step of removing the carrier. 
     
     
         36 . The method of  claim 35 , wherein the first surface of the first substrate includes first and second regions, the conductive elements being exposed at the first surface within the first region and the microelectronic element being attached on the first surface within the second region, and wherein the molded dielectric layer is formed in a first dielectric layer portion and a second dielectric layer portion by the steps of:
 forming the first dielectric layer portion over the first region of the first surface prior to the step of attaching the microelectronic element; and   forming the second dielectric layer portion over the second region of the first surface after the step of attaching the microelectronic element.   
     
     
         37 . The method of  claim 29 , wherein the second subassembly is formed by a method including the step of forming the metal elements on the second surface of the carrier. 
     
     
         38 . The method of  claim 37 , wherein the step of forming the metal elements includes selectively etching a metal layer on a carrier such that selected portions of the metal layer form the metal elements. 
     
     
         39 . The method of  claim 37 , wherein the first subassembly is formed including the steps of affixing a rigid metal layer to the second surface, depositing masses of a bonding metal along selected portions of the rigid metal layer such that first surfaces are defined on the masses of the bonding metal, and removing areas of the rigid metal layer outside of the selected portions thereof. 
     
     
         40 . The method of  claim 39  wherein the steps of forming the first subassembly further include the step of depositing a mask layer over the rigid metal layer, the mask layer having a plurality of openings therethrough that expose the selected portions of the metal layer, and wherein the step of depositing masses of the bonding metal includes depositing the masses within the openings. 
     
     
         41 . The method of  claim 40 , further including the step of removing the mask layer. 
     
     
         42 . The method of  claim 40 , wherein the mask layer acts as at least a portion of an encapsulant layer after the step of transferring the conductive projections. 
     
     
         43 . The method of  claim 39 , wherein the step of attaching the conductive projections includes heating the masses of the bonding metal. 
     
     
         44 . The method of  claim 25 , wherein the microelectronic assembly is formed by the steps of:
 depositing a plurality of masses of a bonding metal on the conductive elements; and   affixing a structure to the plurality of masses, the structure including the carrier and a rigid metal layer, such that the plurality of masses are exposed at selected areas of the rigid metal layer that form the first conductive projections.   
     
     
         45 . The method of  claim 44  further including the step of removing the rigid metal layer outside of the selected areas. 
     
     
         46 . A method for making a microelectronic assembly, comprising:
 aligning first surfaces of rigid metal elements contained in a first microelectronic subassembly with respective conductive elements exposed at first surface of a second microelectronic subassembly, wherein the first microelectronic subassembly includes a first substrate and a plurality of the metal elements removably affixed to the substrate at second surfaces thereof, the first surfaces being remote therefrom;   transferring the metal elements to the second microelectronic subassembly by attaching the first surfaces of the metal elements to the conductive elements of the second microelectronic subassembly and detaching the conductive projections from the first substrate, thereby exposing contact surfaces of the second microelectronic subassembly on the conductive projections remote from the conductive pads; and   attaching a microelectronic element on the second microelectronic subassembly, thereby forming a microelectronic assembly, and electronically connecting the microelectronic element to the conductive pads.   
     
     
         47 . A system comprising a microelectronic assembly according to any one of  claim 1  or  26  and one or more other electronic components electrically connected to the microelectronic assembly. 
     
     
         48 . A system as claimed in  claim 47 , further comprising a housing, said microelectronic assembly and said other electronic components being mounted to said housing.