Non-volatile memory devices and methods of fabricating the same

Abstract

A non-volatile memory device comprises a substrate, a control gate electrode on the substrate, and a charge storage region between the control gate electrode and the substrate. A control gate mask pattern is on the control gate electrode, the control gate electrode comprising a control base gate and a control metal gate on the control base gate. A width of the control metal gate is less than a width of the control gate mask pattern. An oxidation-resistant spacer is at sidewalls of the control metal gate positioned between the control gate mask pattern and the control base gate.

1 . A non-volatile memory device comprising:
 a substrate;   a control gate electrode on the substrate;   a charge storage region between the control gate electrode and the substrate;   a control gate mask pattern on the control gate electrode;   the control gate electrode comprising a control base gate and a control metal gate on the control base gate;   a width of the control metal gate being less than a width of the control gate mask pattern; and   an oxidation-resistant spacer at sidewalls of the control metal gate positioned between the control gate mask pattern and the control base gate.   
     
     
         2 . The non-volatile memory device of  claim 1  wherein a combined width of the control metal gate and a width of the oxidation-resistant spacer at first and second sidewalls of the control metal gate is less than the width of the control gate mask pattern. 
     
     
         3 . The non-volatile memory device of  claim 1  wherein a combined width of the control metal gate and a width of the oxidation-resistant spacer at first and second sidewalls of the control metal gate is equal to the width of the control gate mask pattern. 
     
     
         4 . The non-volatile memory device of  claim 1  wherein a width of the oxidation-resistant spacer is less than one-half a width of a narrowest portion of the control metal gate. 
     
     
         5 . The non-volatile memory device of  claim 1  further comprising a lower barrier layer pattern between the control base gate and the control metal gate. 
     
     
         6 . The non-volatile memory device of  claim 5  wherein the lower barrier layer pattern is of a thickness that is less than one-half a thickness of the control metal gate. 
     
     
         7 . The non-volatile memory device of  claim 5  wherein the lower barrier layer pattern is of a width that is less than the width of the control gate mask pattern. 
     
     
         8 . The non-volatile memory device of  claim 1  further comprising an upper barrier layer pattern between the control metal gate and the gate mask pattern. 
     
     
         9 . The non-volatile memory device of  claim 8  wherein the upper barrier layer pattern is of a thickness that is less than one-half a thickness of the control metal gate. 
     
     
         10 . The non-volatile memory device of  claim 8  wherein the upper barrier layer pattern is of a width that is less than the width of the control gate mask pattern. 
     
     
         11 . The non-volatile memory device of  claim 1  wherein the control base gate includes a lower portion and an upper portion, wherein the upper portion is of a width that is less than a width of the lower portion. 
     
     
         12 . The non-volatile memory device of  claim 11  wherein the oxidation resistant spacer covers a top surface and sidewall surface of the upper portion of the control base gate. 
     
     
         13 . The non-volatile memory device of  claim 1  further comprising an insulative layer on the control gate electrode. 
     
     
         14 . The non-volatile memory device of  claim 13  wherein a memory cell region of the memory device includes multiple control gate electrodes, and wherein air gaps are present in the insulative layer between neighboring control gate electrodes. 
     
     
         15 . The non-volatile memory device of  claim 1  wherein the charge storage region comprises a tunnel dielectric layer on the substrate, a floating gate on the tunnel dielectric layer and a blocking layer on the floating gate. 
     
     
         16 . The non-volatile memory device of  claim 15  wherein the floating gate and blocking layer are patterned to have sidewalls that are aligned with sidewalls of the control base gate. 
     
     
         17 . The non-volatile memory device of  claim 15  further comprising an oxidation layer on the sidewalls of the floating gate. 
     
     
         18 . The non-volatile memory device of  claim 1  wherein the charge storage region comprises a tunnel dielectric layer on the substrate, a dielectric charge storage layer on the tunnel dielectric layer and a blocking layer on the dielectric charge storage layer. 
     
     
         19 . The non-volatile memory device of  claim 18  wherein the charge-storage region comprises a ONO-type structure 
     
     
         20 . The non-volatile memory device of  claim 18  wherein the dielectric charge storage layer and the blocking layer are patterned to have sidewalls that are aligned with sidewalls of the control base gate. 
     
     
         21 . The non-volatile memory device of  claim 1  further comprising an oxidation layer on sidewalls of the control base gate. 
     
     
         22 . The non-volatile memory device of  claim 1  wherein the memory device comprises a memory cell region and wherein the control gate electrode and the control gate mask pattern are located in the memory cell region and wherein the memory device further comprises a peripheral region including:
 a peripheral gate electrode on the substrate in the peripheral region; 
 the peripheral gate electrode comprising a peripheral base gate and a peripheral metal gate on the peripheral base gate; 
 a peripheral gate mask pattern on the peripheral gate electrode; 
 a width of the peripheral metal gate being less than a width of the peripheral gate mask pattern; and 
 an oxidation-resistant spacer at sidewalls of the peripheral metal gate and below the peripheral gate mask pattern. 
 
     
     
         23 . The non-volatile memory device of  claim 22  wherein the peripheral base gate is a same material as the control base gate, wherein the peripheral metal gate is a same material as the control metal gate, and wherein the oxidation-resistant spacer at sidewalls of the peripheral metal gate is a same material as the oxidation-resistant spacer at sidewalls of the control metal gate. 
     
     
         24 . The non-volatile memory device of  claim 22  wherein a thickness of the oxidation-resistant spacer at sidewalls of the peripheral metal gate is greater than a thickness of the oxidation-resistant spacer at sidewalls of the control metal gate. 
     
     
         25 . The non-volatile memory device of  claim 22  wherein at least one of the control base gate and the peripheral base gate includes a lower portion and an upper portion, wherein the upper portion is of a width that is less than a width of the lower portion. 
     
     
         26 . The non-volatile memory device of  claim 22  wherein the peripheral gate electrode further comprises:
 a peripheral bottom gate on the substrate between the peripheral base gate and the substrate; 
 a peripheral gate dielectric layer between the peripheral bottom gate and the substrate; and 
 an interlayer dielectric layer pattern between the peripheral base gate and the peripheral bottom gate, 
 wherein the peripheral metal gate directly contacts the peripheral bottom gate through an opening in the peripheral base gate and in the dielectric layer pattern. 
 
     
     
         27 . The non-volatile memory device of  claim 1  wherein the oxidation-resistant spacer comprises nitride. 
     
     
         28 . The non-volatile memory device of  claim 27  wherein the oxidation-resistant spacer comprises insulating nitride. 
     
     
         29 . The non-volatile memory device of  claim 28  wherein the oxidation-resistant spacer comprises a material selected from the group consisting of silicon nitride and silicon oxynitride. 
     
     
         30 . The non-volatile memory device of  claim 27  wherein the oxidation-resistant spacer comprises conductive nitride. 
     
     
         31 . The non-volatile memory device of  claim 30  wherein the oxidation-resistant spacer comprises a material selected from the group consisting of metal nitride, titanium nitride, tantalum nitride, and tungsten nitride. 
     
     
         32 . The non-volatile memory device of  claim 1  wherein a height of the oxidation-resistant spacer is equal to a height of the control metal gate. 
     
     
         33 .- 70 . (canceled)