System-level emulation/verification system and system-level emulation/verification method

Abstract

A system-level emulation/verification system includes an operating device for using a simulator to set soft intellectual properties (soft IPs) corresponding to a System-on-Chip (SOC) design module, executing a simulation corresponding to the SOC design module, and using a transactor to interact with the simulator via an Application Programming Interface (API); and a hard-wired based platform, including a hard IP corresponding to a soft IP of the SOC design module, wherein the hard-wired based platform sets the hard IP according to a setting of the SOC design module, and outputs an operating result of the hard IP corresponding to the setting of the SOC design module. The hard-wired based platform executes an IP model proxy for receiving an output of the transactor, transmitting the output to the hard-wired platform for controlling the operation of the hard IP, and transmitting the operating result to the transactor executed by the operating device.

1 . A system-level emulation/verification system, comprising:
 an operating device, for executing a plurality of software modules, the software modules comprising:
 a simulator, for setting soft intellectual properties (soft IPs) corresponding to a System-on-Chip (SOC) design module, and executing a simulation corresponding to the SOC design module; and 
 a transactor, interacting with the simulator via an Application Programming Interface (API); 
   a hard-wired based platform, comprising:
 at least a hard IP, corresponding to a soft IP of the soft IPs within the SOC design module, wherein the hard-wired based platform sets the hard IP according to a setting corresponding to the SOC design module and outputs an operating result of the hard IP and the operating result corresponds to the setting of the hard IP, in addition, the hard-wired based platform executes an IP module proxy for receiving an output of the transactor from a message channel, transmitting the output of the transactor to the hard-wired based platform for controlling the hard IP, and transmitting the operating result of the hard IP to the transactor via the message channel, wherein the transactor is executed by the operating device; and 
   a serial link, coupled to the operating device and the hard-wired based platform, for providing the message channel connecting the operating device and the hard-wired based platform.   
     
     
         2 . The system-level emulation/verification system of  claim 1 , wherein the hard-wired based platform operates the hard IP at a silicon-level speed, and the hard IP corresponds to the soft IP of the soft IPs within the SOC design module. 
     
     
         3 . The system-level emulation/verification system of  claim 1 , wherein the operating device executes the simulation of the SOC design module by using the simulator to execute a test bench; after the simulator instantiates each of the soft IPs to which the SOC design module corresponds, the simulator executes the simulation corresponding to the SOC design module; and, the setting of the SOC design module comprises settings of each of the soft IPs so that the hard-wired based platform sets the hard IP according to the setting of the corresponding soft IP of the soft IPs. 
     
     
         4 . The system-level emulation/verification system of  claim 1 , wherein the operating device uses the transactor for interacting with the IP module proxy via the message channel, and the operating device translates messages of the simulators by executing the transactor, and transmits the messages to the hard-wired based platform via the IP module proxy. 
     
     
         5 . The system-level emulation/verification system of  claim 4 , wherein the API corresponds to an Advanced Microcontroller Bus Architecture-Advanced High-Performance Bus (AMBA-AHB). 
     
     
         6 . The system-level emulation/verification system of  claim 1 , wherein the system-level emulation/verification system complies with a specification of Standard Co-Emulation Modeling Interface (SCE-MI). 
     
     
         7 . The system-level emulation/verification system of  claim 1 , wherein emulations and verifications of a whole circuit system are executed before executing a tape-out operation of the whole circuit system. 
     
     
         8 . A system-level emulation/verification method, comprising:
 setting soft intellectual properties (soft IPs) within a simulator, corresponding to a SOC design module, and using the simulator for executing a simulation corresponding to the SOC design module;   using a transactor for interacting with the simulator via an Application programming Interface (API);   using a hard-wired based platform which comprises at least a hard IP, for setting the hard IP according to a setting corresponding to the SOC design module, and outputting an operating result of the hard IP accordingly, wherein the hard IP corresponds to a soft IP of the soft IPs within the SOC design module; and   receiving an output of the transactor via a message channel, transmitting the output of the transactor to the hard-wired based platform for operating the hard IP accordingly, and transmitting the operating result of the hard IP to the transactor via the message channel.   
     
     
         9 . The system-level emulation/verification method of  claim 8 , which operates the simulation corresponding to the SOC design module at a silicon-level speed. 
     
     
         10 . The system-level emulation/verification method of  claim 8 , wherein the step of using the simulator for executing the simulation corresponding to the SOC design module executes the simulation corresponding to the SOC design module by executing a test bench by the simulator; the step of setting the soft IPs corresponding to the SOC design module within the simulator comprises:
 after the simulator instantiating each of the soft IPs to which the SOC design module corresponds, the simulator executes the simulation corresponding to the SOC design module; wherein the setting of the SOC design module comprises settings of each of the soft IPs so that the hard-wired based platform sets the hard IP according to the setting of the corresponding soft IP of the soft IPs.   
     
     
         11 . The system-level emulation/verification method of  claim 8 , wherein the step of using the transactor for interacting with the simulator via the API comprises:
 translating messages of the simulator and transmitting the messages via the message channel.   
     
     
         12 . The system-level emulation/verification method of  claim 11 , wherein the API corresponds to an Advanced Microcontroller Bus Architecture-Advanced High-Performance Bus (AMBA-AHB). 
     
     
         13 . The system-level emulation/verification method of  claim 8 , wherein the system-level emulation/verification system complies with a specification of Standard Co-Emulation Modeling Interface. 
     
     
         14 . The system-level emulation/verification method of  claim 8 , being executed before executing a tape-out operation of a corresponding whole circuit system.