Semiconductor device and method for fabricating the same

Abstract

The present invention relates to a semiconductor and manufacturing method thereof, in which a nano tube structure is vertically grown to form a lower electrode of a cell region and a via contact of peripheral circuit region. Therefore, capacitance of the lower electrode is secured without an etching process for high aspect ratio. Also, the via contact can be formed for corresponding to the height of the lower electrode.

1 . A method of fabricating a semiconductor device, the method comprising:
 forming a bit line and a bit line pad in a cell region and a peripheral region, respectively, over a substrate;   forming a first metal layer on the bit line and the bit line pad;   forming an interlayer insulating film over the first metal layer and the substrate;   etching the interlayer insulating film in the cell region to form a storage node contact hole;   filling the storage node contact hole with conductive material to form a storage node contact plug in the cell region;   forming a second metal layer over the storage node contact plug;   etching the interlayer insulating film in the peripheral region to form a contact hole exposing the first metal layer over the bit line pad;   growing a nano tube using the second metal layer in the cell region and the exposed first metal layer in the peripheral region as a catalyst to form a lower electrode and a first contact, respectively; and   forming a second contact connected to the first contact in the peripheral region to form a via contact.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a dielectric film over a surface of the interlayer insulating film and the lower electrode; and   forming an upper electrode over a surface of the dielectric film,   wherein the lower electrode, the dielectric film, and the upper electrode define a capacitor.   
     
     
         3 . The method of  claim 1 , wherein the first metal layer and the second metal layer includes one selected from the group consisting of Ni, Co, Fe, La, Ti, Y, Pd, Pt and combinations thereof. 
     
     
         4 . The method of  claim 1 , wherein the uppermost surface of the storage node contact plug is lower than the upper most surface of the interlayer insulating film to provide a height difference between the storage node contact plug and the interlayer insulating film. 
     
     
         5 . The method of  claim 4 , wherein the forming the second metal layer comprises:
 forming a metal catalyst material over the storage node contact plug and the interlayer insulating film; and   polishing the metal catalyst material until the interlayer insulating film is exposed, where the metal catalyst material and the interlayer insulating film define a planar surface without a substantial height difference.   
     
     
         6 . The method of  claim 1 , wherein the nano tube is grown using a chemical vapor deposition (CVD) process. 
     
     
         7 . The method of  claim 1 , wherein the nano tube is a carbon nano tube, a Si nano tube or a Ge nano tube. 
     
     
         8 . The method of  claim 7 , wherein the carbon nano tube is grown by using CH 4 , C 2 H 2 , ethanol or CO gas at a temperature of 300˜900° C. 
     
     
         9 . The method of  claim 7 , wherein the Si nano tube is grown by using a gas containing SiH 4  or Si 2 H 6  at a temperature of 300˜900° C. 
     
     
         10 . The method of  claim 7 , wherein the Ge nano tube is grown by using Ge containing gas at a temperature of 300˜900° C. 
     
     
         11 . The method of  claim 1 , further comprising forming a dielectric film and an upper electrode over the lower electrode and the interlayer insulating film. 
     
     
         12 . The method of  claim 1 , further comprising forming a metal wiring connected to the second contact,
 wherein the conductive material partly fills the storage node contact hole to provide a height difference between the interlayer insulating layer and the storage node contact plug.