Systems and methods integrating boolean processing and memory

Abstract

The present disclosure relates to placing a Boolean Processor on a chip with memory to eliminate memory latency issues in computing systems. An asynchronous implementation of a Boolean Processor Switched Memory can theoretically operate at terahertz speed and vastly improve the rate at which computationally relevant data is fed to a microprocessor or microcontroller. Boolean Processor Enhanced Memories hold the promise of increasing memory throughput by several orders of magnitude and shifting the burden of “catching up” to microprocessors and microcontrollers.

1 . An integrated circuit forming a memory module connected to a microprocessor, comprising:
 a plurality of memory segments configured to store data;   a Boolean Processor unit in communication with the plurality of memory segments; and   a plurality of input/output interfaces in communication with the plurality of memory segments, the Boolean Processor, and the microprocessor;   wherein the Boolean Processor unit is configured to qualify data for the microprocessor from the plurality of memory segments responsive to the instructions.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the Boolean Processor unit comprises:
 a Boolean logic unit, wherein the Boolean logic unit is operated for performing the short-circuit evaluation of a Normal Form Boolean expression/operation;   a second plurality of input/output interfaces in communication with the Boolean logic unit, wherein the second plurality of input/output interfaces are operated for receiving a plurality of compiled Boolean expressions/operations and transmitting a plurality of compiled results; and   a plurality of registers coupled to the second plurality of input/output interface circuits, wherein the plurality of multi-bit registers comprise an instruction register, a first address register and a second address register.   
     
     
         3 . The integrated circuit of  claim 1 , wherein the integrated circuit is implemented in an asynchronous mode as one of clockless or self-clocking. 
     
     
         4 . The integrated circuit of  claim 1 , further comprising:
 a memory switching architecture comprising memory segment switching circuitry, wherein the memory segment switching circuitry is in communication with the plurality of input/output interfaces, the plurality of memory segments, and the Boolean Processor unit.   
     
     
         5 . The integrated circuit of  claim 4 , wherein the memory segment switching circuitry is configured to:
 connect the Boolean Processor unit to a first segment of the plurality of memory segments at any given point in time;   switch the Boolean Processor unit to a second segment of the plurality of memory segments responsive to a trigger from the Boolean Processor unit; and   connect a third segment of the plurality of memory segments to the plurality of input/output interfaces for buffering incoming data.   
     
     
         6 . The integrated circuit of  claim 5 , further comprising:
 a first segment address register in the memory segment switching circuitry being indicative of one of the plurality of memory segments to connect to the Boolean Processor unit; and   a second segment address register in the memory segment switching circuitry being indicative of one of the plurality of memory segments to connect to the plurality of input/output interfaces.   
     
     
         7 . The integrated circuit of  claim 6 , wherein the Boolean Processor unit comprises:
 an offset register for indicating a starting address within one of the plurality of memory segments; and   a counter for maintaining read and write block sizes.   
     
     
         8 . The integrated circuit of  claim 1 , wherein the Boolean Processor unit comprises an n-bit processor, wherein each of the memory segments comprises m bytes, and wherein the plurality of memory segments comprises a total of x bytes, n, m, and x comprise an integer. 
     
     
         9 . The integrated circuit of  claim 1 , wherein a size of the Boolean Processor unit is selected to closely match a speed of the integrated circuitry. 
     
     
         10 . The integrated circuit of  claim 1 , wherein the integrated circuitry operates in excess of 1 THz speed in qualifying data in the plurality of memory segments utilizing the Boolean Processor unit. 
     
     
         11 . The integrated circuit of  claim 1 , further comprising:
 an algorithm operable through the Boolean Processor unit for matching sub-bytes in the plurality of memory segments, wherein the algorithm provides a search of any value contained with n bits in the plurality of memory segments.   
     
     
         12 . The integrated circuit of  claim 1 , further comprising:
 an algorithm operable through the Boolean Processor unit for repetitively matching contents of one or more bytes in the plurality of memory segments, wherein each match is output to the plurality of input/output interfaces, and wherein the algorithm is configured to cycle through each of the plurality of memory segments.   
     
     
         13 . A Boolean Processor Switched Memory, comprising:
 a Boolean Processor receiving instructions from an external device and sending data to the external device based on the instructions;   a plurality of memory segments; and   memory segment switching circuitry connected to the Boolean Processor and the plurality of memory segments;   wherein the Boolean Processor is configured to receive instructions from the external device and transmit data based on the instructions from the plurality of memory segments.   
     
     
         14 . The Boolean Processor Switched Memory of  claim 13 , wherein the memory segment switching circuitry is configured to:
 connect the Boolean Processor to a first segment of the plurality of memory segments at any given point in time;   switch the Boolean Processor to a second segment of the plurality of memory segments responsive to a trigger from the Boolean Processor; and   connect a third segment of the plurality of memory segments to an incoming data source for buffering incoming data.   
     
     
         15 . The Boolean Processor Switched Memory of  claim 14 , further comprising:
 a first segment address register in the memory segment switching circuitry being indicative of one of the plurality of memory segments to connect to the Boolean unit; and   a second segment address register in the memory segment switching circuitry being indicative of one of the plurality of memory segments to connect to the incoming data source.   
     
     
         16 . The Boolean Processor Switched Memory of  claim 15 , wherein the Boolean Processor comprises:
 a Boolean logic unit, wherein the Boolean logic unit is operated for performing the short-circuit evaluation of a Normal Form Boolean expression/operation;   a plurality of input/output interfaces in communication with the Boolean logic unit, wherein the plurality of input/output interfaces are operated for receiving a plurality of compiled Boolean expressions/operations and transmitting a plurality of compiled results; and   a plurality of registers coupled to the plurality of input/output interface circuits, wherein the plurality of multi-bit registers comprise an instruction register, a first address register, a second address register, and an offset register for indicating a starting address within one of the plurality of memory segments; and   a counter for maintaining read and write block sizes.   
     
     
         17 . The Boolean Processor Switched Memory of  claim 13 , further comprising:
 an algorithm operable through the Boolean Processor for matching sub-bytes in the plurality of memory segments, wherein the algorithm provides a search of any value contained with n bits in the plurality of memory segments.   
     
     
         18 . The Boolean Processor Switched Memory of  claim 13 , further comprising:
 an algorithm operable through the Boolean Processor for repetitively matching contents of one or more bytes in the plurality of memory segments, wherein each match is output to the external device, and wherein the algorithm is configured to cycle through each of the plurality of memory segments.   
     
     
         19 . A method, comprising:
 at a memory module comprising an integrated Boolean Processor, receiving an instruction related to qualifying data in the memory module;   generating a Boolean operation based on the instruction;   evaluating the Boolean operation on data in the memory module; and   providing qualified data based on the evaluation to an external device from the memory module.   
     
     
         20 . The method of  claim 19 , wherein generating and evaluating the Boolean operation comprises:
 receiving a Normal Form Boolean expression, wherein the Normal Form Boolean expression comprises a conjunct or a disjunct;   evaluating the conjunct or disjunct;   selectively short-circuiting a portion of the Normal Form Boolean expression; and   outputting a result of the Normal Form Boolean expression.