Data storage device

Abstract

A data storage device comprising: at least two flash devices for storing data; a circuit board, wherein each of the flash devices are integrated on the circuit board; a controller integrated on the circuit board for reading and writing to each flash devices, wherein the controller interfaces each flash devices; at least one NOR Flash device in communication with the controller through a host bus; at least one host bus memory device in communication with the controller and at least one NOR Flash device through the host bus; at least one interface in communication with the controller and adapted to physically and electrically couple to a system, receive and store data therefrom and retrieve and transmit data to the system.

1 . A data storage device comprising:
 at least two flash devices;   a controller, wherein said controller interfaces each said at least two flash devices;   at least one NOR Flash device in communication with said controller through an independent host bus;   at least one host bus memory device in communication with said controller through said independent host bus;   at least one interface in communication with said controller and a computing system,   wherein said controller is adapted to communicate with all the flash devices simultaneously, and   wherein the host bus is utilized for communication between the controller and exclusively the NOR Flash device and the host bus memory device.   
     
     
         2 . The data storage device of  claim 1 , said controller further comprising a bad-block module, wherein said bad-block module detects bad blocks in each said at least two flash devices during operation of said data storage devices 
     
     
         3 . The data storage device of  claim 1 , further comprising Static Random Access Memory (SRAM) in communication with said controller. 
     
     
         4 . The data storage device of  claim 1 , wherein said controller comprises at least one programmable microprocessor and further comprising an interface for interfacing said controller with each flash device and wherein said at least one programmable microprocessor consist of seventeen (17) programmable microprocessors and wherein each said interface is controlled by an autonomous microprocessor. 
     
     
         5 . The data storage device of  claim 1 , wherein the controller is further comprised of a bad-block module, wherein said bad-block module detects bad blocks in each said at least one flash device during operation of said data storage devices. 
     
     
         6 . The data storage device of  claim 7 , wherein said bad-block module detects bad blocks in each said at least one flash device concurrently. 
     
     
         7 . The data storage device of  claim 1 , further comprising a NOR Flash drive in communication with said controller. 
     
     
         8 . The data storage device of  claim 9 , further comprising at least one programmable microprocessor, wherein said NOR flash is adaptively coupled to said at least one programmable microprocessors and said controller, wherein said NOR flash has at least one code of said programmable microprocessor. 
     
     
         9 . The data storage device of  claim 8 , wherein said NOR flash drive contains the Operating System (OS) that provides control of the main microprocessor(s). 
     
     
         10 . The data storage device of  claim 11 , wherein said controller is a FPGA based NAND Flash controller and said microprocessor initializes, controls, provisions, maintains, and diagnoses the Flash devices and internal registers of the FPGA. 
     
     
         11 . The data storage device of  claim 1 , wherein said controller further comprises a sleep-mode module, wherein said sleep-mode module enables sleep mode for said at least one flash device based on a predefined criterion. 
     
     
         12 . The data storage device of  claim 1 , wherein said controller further comprises a prevention module for controlling the wear level of each said at least one flash device. 
     
     
         13 . The data storage device of  claim 1 , wherein said controller further comprises write-protection module, wherein said write-protection module provides write protection on each said at least one flash device. 
     
     
         14 . The data storage device of  claim 1 , wherein said controller reads and writes to each flash device concurrently. 
     
     
         15 . The data storage device of  claim 1 , further comprising at least two die, wherein said at least two die may be concurrently accessed. 
     
     
         16 . The data storage device of  claim 1 , wherein the controller divides data into a plurality of data blocks, at least one data block is stored in a flash device from the plurality of flash devices. 
     
     
         17 . The data storage device of  claim 1 , wherein at least one said flash device is a single level cell (SLC) NAND flash device. 
     
     
         18 . The data storage device of  claim 1 , further comprising Synchronous Dynamic Access Memory (SDRAM) in communication with said controller. 
     
     
         19 . The data storage device of  claim 1 , wherein said controller interfaces each said at least two flash devices individually through an independent NAND bus 
     
     
         20 . The data storage device of  claim 1 , further comprising a circuit board, wherein each said at least two flash devices and said controller are integrated on said circuit board; 
     
     
         21 . The data storage device of  claim 1 , wherein each flash device is a chip adapted for including at least two dies.