Structures and methods for improving solder bump connections in semiconductor devices

Abstract

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

1 . A method of manufacturing a semiconductor structure, comprising:
 forming a SiN layer;   forming a flurosilicate glass (FSG) layer on the SiN layer;   forming a trench in the FSG layer such that the trench extends only partially through the FSG layer; and   forming a copper wire in the trench such that an entire bottom portion of the copper wire is embedded in the FSG layer, wherein the entire bottom portion of the copper wire in the trench only has an interface with the FSG layer and the interface between the FSG layer and the bottom portion of the copper wire is devoid of a fluorine boundary layer.   
     
     
         2 . The method of  claim 1 , further comprising denuding the trench of fluorine such that the copper wire is in contact with a non-fluoride layer of the trench. 
     
     
         3 . The method of  claim 2 , wherein the denuding comprises exposing the trench to one of NH 3 , SiH 4 /NH 3 , and SiH 4 /NH 3 /N 2  plasma, prior to the forming of the copper wire. 
     
     
         4 . The method of  claim 2 , wherein the denuding comprises exposing the trench to a hydrogen or ammonia plasma prior to the forming of the copper wire. 
     
     
         5 . The method of  claim 1 , further comprising depositing a SiO 2  layer in the trench prior to the forming of the copper wire. 
     
     
         6 . The method of  claim 5 , wherein the SiO 2  layer is about 50 nm in thickness. 
     
     
         7 . The method of  claim 1 , further comprising depositing an undoped silicate glass (USG) layer interposed between the SiN layer and the FSG layer. 
     
     
         8 . The method of  claim 1 , further comprising:
 depositing a second SiN layer over the FSG layer;   depositing an SiO 2  layer on the second SiN layer;   forming a via trench in the second SiN layer and the SiO 2  layer to the copper wire;   forming a wire of TaN/TiN/AlCu/TiN in the via trench, where the AlCu thickness is greater than the TaN and TiN thickness, wherein the wire makes electrical contact with the copper wire;   forming a dielectric layer over the wire and the SiO 2  layer;   forming a trench in the dielectric layer and the wire; and   forming a Pb-free solder bump in the trench formed in the dielectric layer and the wire.   
     
     
         9 . The method of  claim 8 , wherein the trench in the dielectric layer and the solder bump are formed over the trench in the FSG layer. 
     
     
         10 . The method of  claim 1 , further comprising forming a solder bump in electrical contact with the copper wire in the trench.