Circuit board with via trace connection and method of making the same

Abstract

Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor trace with a first segment that does not include a via land. A first via is formed on the first segment.

1 . A method of manufacturing, comprising:
 forming a first interconnect layer of a circuit board, the first interconnect layer including a first conductor trace with a first segment that includes a first protuberance, the first protuberance having a first footprint; and   forming a first via on the first protuberance, the first via having a second footprint larger than the first footprint.   
     
     
         2 . The method of  claim 1 , wherein the first via is formed with a notch to seat over the first protuberance. 
     
     
         3 . The method of  claim 1 , wherein the first protuberance comprises a rounded cap. 
     
     
         4 . The method of  claim 1 , comprising forming second and third conductor traces in the first interconnect layer in spaced apart relation and offset laterally from the first via. 
     
     
         5 . The method of  claim 4 , comprising forming a fourth conductor trace in the first interconnect layer in spaced apart relation to the first conductor trace, the fourth conductor trace including a second segment that includes a second protuberance, the second protuberance having a third footprint, and forming a second via on the second protuberance, the second via having a fourth footprint larger than the third footprint. 
     
     
         6 . The method of  claim 1 , comprising coupling a semiconductor chip to the circuit board. 
     
     
         7 . The method of  claim 1 , comprising forming the first conductor trace and first via using instructions stored in a computer readable medium. 
     
     
         8 . The method of  claim 1 , comprising forming a second interconnect layer on the first interconnect layer. 
     
     
         9 . A method of conveying current in a circuit board, comprising:
 positioning a first via on a first segment of a first conductor trace in a first interconnect layer of the circuit board, the first via having a first footprint, the first segment including a first protuberance having a second footprint smaller than the first footprint; and   conveying a first current through the first conductor trace and the first via.   
     
     
         10 . The method of  claim 9 , wherein the first current comprises electrical signals. 
     
     
         11 . The method of  claim 9 , comprising positioning a second via having a third footprint on a second segment of a second conductor trace in the first interconnect layer wherein the second segment includes a second protuberance having a fourth footprint smaller than the third footprint, and conveying a second current through the second via and the second conductor trace. 
     
     
         12 . The method of  claim 11 , positioning third and fourth conductor traces in spaced apart relation between the first and second vias and conveying a third current through at least one of the third and fourth conductor traces. 
     
     
         13 . The method of  claim 12 , wherein the circuit board comprises a semiconductor chip, the method comprising using the third and fourth conductor traces to convey the third current between the semiconductor chip and the circuit board. 
     
     
         14 . A circuit board, comprising:
 a first interconnect layer including a first conductor trace with a first segment that includes a first protuberance, the first protuberance having a first footprint; and   a first via on the first protuberance, the first via having a second footprint larger than the first footprint.   
     
     
         15 . The circuit board of  claim 14 , comprising a second conductor trace in the first interconnect layer in spaced apart relation to the first conductor trace, the second conductor trace including a second segment includes a second protuberance having a third footprint, and a second via on the second protuberance and having a fourth footprint larger than the third footprint. 
     
     
         16 . The circuit board of  claim 14 , comprising third and fourth conductor traces in the first interconnect layer in spaced apart relation and offset laterally from the first via. 
     
     
         17 . The circuit board of  claim 14 , wherein the first via comprises a notch to seat over the first protuberance. 
     
     
         18 . The circuit board of  claim 14 , wherein the first protuberance comprises a rounded cap. 
     
     
         19 . The circuit board of  claim 14 , comprising a semiconductor chip coupled to the circuit board.