US2012119215A1PendingUtilityA1

Array substrate, method of manufacturing the array substrate, and liquid crystal display device having the array substrate

Assignee: YOU HYE-RANPriority: Jul 28, 2008Filed: Jan 13, 2012Published: May 17, 2012
Est. expiryJul 28, 2028(~2 yrs left)· nominal 20-yr term from priority
G02F 1/1343G02F 1/1393G02F 1/133707G02F 1/13606
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Claims

Abstract

In an array substrate, a method of manufacturing the array substrate, and a liquid crystal display (LCD) device having the array substrate, a pixel electrode includes an outline portion, connection portions, and slit portions. The outline portion is arranged toward a data line and a gate line thereon, and the connection portions extend in a direction that crosses the data line and the gate line, respectively, to connect to the outline portion. The slit portions protrude from side surfaces of the connection portions to connect to the outline portion. A shielding electrode is arranged toward the outline portion between the data line and the outline portion, and the gate line and the outline portion.

Claims

exact text as granted — not AI-modified
1 . An array substrate comprising:
 a substrate comprising a gate line and a data line that cross each other and that are insulated from each other, and a switching element connected to the gate line and the data line ;   a pixel electrode comprising:
 an outline portion arranged on the substrate along the data line and the gate line, 
 a plurality of connection portions that extend in a crossing direction of the data line and the gate line, and connect to the outline portion, the connection portions dividing a pixel area defined by the outline portion into a plurality of domains, and 
 a plurality of slit portions that protrude from side surfaces of the connection portions in each of the domains, the slit portions being connected to the outline portion; and 
   a shielding electrode arranged along the outline portion on the data line and the outline portion on the gate line and shielding the data line and the gate line, respectively, wherein the shielding electrode is arranged between the data line and the outline portion.

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