Image capture device with four processing units

Abstract

An image capture device that has an image sensor, a RISC core, four processing units connected in parallel to the RISC core via a data cache, the four processing units being interconnected with a crossbar switch and an image sensor interface. The image sensor interface is configured to receive image data from the image sensor for parallel processing by the four processing units in accordance with processing instructions from the RISC core.

1 . An image capture device comprising:
 an image sensor;   a RISC core;   four processing units connected in parallel to the RISC core via a data cache, the four processing units being interconnected with a crossbar switch; and,   an image sensor interface configured to receive image data from the image sensor for parallel processing by the four processing units in accordance with processing instructions from the RISC core.   
     
     
         2 . The image capture device according to  claim 1  wherein the RISC core, the four processing units and the image sensor interface are a integrated into a single central processor which is in the form of an application specific integrated circuit (ASIC). 
     
     
         3 . The image capture device according to  claim 1  wherein the RISC core is configured to run an image processing language interpreter. 
     
     
         4 . The image capture device according to  claim 2  wherein each of the processing units has microcode RAM such that during use, the RISC processor write processing instructions to the RAM. 
     
     
         5 . The image capture device according to  claim 4  wherein the central processor has DRAM to read and write between the core and the processing units. 
     
     
         6 . The image capture device according to  claim 5  wherein the central processor has cache memory for an image processing program to be accessed by the RISC core. 
     
     
         7 . The image capture device according to  claim 2  further comprising an image scanner wherein the central processor has a scanner interface to permit data scanned by the image scanner to be communicated to the core.