Bipolar and FET Device Structure

Abstract

A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT.

1 . A semiconductor structure, comprising:
 a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer comprising a semiconductor material; and   a field effect transistor (FET) located over the substrate, the FET comprising a channel formed in the semiconductor material that forms the collector layer of the HBT.   
     
     
         2 . The semiconductor structure of  claim 1 , in which the semiconductor material that forms the collector layer of the HBT and the channel of the FET comprises p-type gallium arsenide. 
     
     
         3 . The semiconductor structure of  claim 1 , further comprising an etch stop layer segment located over the collector layer of the HBT and the channel of the FET. 
     
     
         4 . The semiconductor structure of  claim 3 , wherein the etch stop layer comprises indium gallium arsenide. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein the etch stop layer has a thickness range between 10 nanometers (nm) and 15 nm 
     
     
         6 . A semiconductor structure, comprising:
 a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate and an emitter layer located over the substrate, the collector layer comprising a first semiconductor material of a first conductivity type (P), the emitter layer comprising a second semiconductor material of a second conductivity type (N);   a first field effect transistor (FET) located over the substrate, the first FET comprising a channel formed in the first semiconductor material that forms the collector layer of the HBT; and   a second field effect transistor (FET) located over the substrate, the second FET comprising a channel formed in the second semiconductor material that forms the emitter layer of the HBT.   
     
     
         7 . The semiconductor structure of  claim 6 , in which:
 the first semiconductor material that forms the collector layer of the HBT and the channel of the first FET comprises p-type gallium arsenide; and   the second semiconductor material that forms the emitter layer of the HBT and the channel of the second FET comprises n-type gallium arsenide.   
     
     
         8 . The semiconductor structure of  claim 6 , further comprising:
 a first etch stop layer segment located over the collector layer of the HBT and the channel of the first FET; and   a second etch stop layer segment located over the emitter layer of the HBT and the channel of the second FET.   
     
     
         9 . The semiconductor structure of  claim 8 , wherein the first etch stop layer segment and the second etch stop layer segment comprise indium gallium arsenide. 
     
     
         10 . The semiconductor structure of  claim 9 , wherein the first etch stop layer segment and the second etch stop layer segment have a thickness range between 10 nanometers (nm) and 15 nm 
     
     
         11 . A method, comprising:
 forming a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate and an emitter layer located over the substrate, the collector layer comprising a first semiconductor material of a first conductivity type (P), the emitter layer comprising a second semiconductor material of a second conductivity type (N);   forming a first field effect transistor (FET) over the substrate, the first FET comprising a channel formed in the first semiconductor material that forms the collector layer of the HBT; and   forming a second field effect transistor (FET) over the substrate, the second FET comprising a channel formed in the second semiconductor material that forms the emitter layer of the HBT.   
     
     
         12 . The method of  claim 11 , further comprising:
 forming the first semiconductor material that forms the collector layer of the HBT and the channel of the first FET using p-type gallium arsenide; and   forming the second semiconductor material that forms the emitter layer of the HBT and the channel of the second FET using n-type gallium arsenide.   
     
     
         13 . The method of  claim 11 , further comprising:
 forming a first etch stop layer segment over the collector layer of the HBT and the channel of the first FET; and   forming a second etch stop layer segment over the emitter layer of the HBT and the channel of the second FET.   
     
     
         14 . The method of  claim 13 , further comprising forming the first etch stop layer segment and the second etch stop layer segment using indium gallium arsenide. 
     
     
         15 . The method of  claim 14 , further comprising forming the first etch stop layer segment and the second etch stop layer segment to a thickness range between 10 nanometers (nm) and 15 nm.