Trench metal oxide semiconductor field effect transistor (MOSFET) with low gate to drain coupled charges (Qgd) structures

Abstract

A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further comprises tilt-angle implanted body dopant regions surrounding a lower portion of trench sidewalls for reducing a gate-to-drain coupling charges Qgd between the trenched gates and a drain disposed at a bottom of the semiconductor substrate. The trenched semiconductor power device further includes a source dopant region disposed below a bottom surface of the trenched gates for functioning as a current path between the drain to the source for preventing a resistance increase caused by the body dopant regions surrounding the lower portions of the trench sidewalls.

1 . A method for manufacturing a trenched semiconductor power device on a semiconductor substrate comprising:
 opening a plurality of trenches from a top surface of said semiconductor substrate; and   carrying out a tilt-angle body-dopant implantation through sidewalls of trenches to form body dopant regions surrounding sidewalls of said trenches followed by carrying out a vertical source dopant implant to form a source dopant region below a bottom surface of said trenches.   
     
     
         2 . The method of  claim 1  wherein:
 said step of carrying out said tilt-angle body dopant implantation through said sidewalls of said trenches further comprising a step of carrying out a tilt angle body dopant implantation with a tilt-angle ranging between 4 to 45 degrees. 
 
     
     
         3 . The method of  claim 1  further comprising:
 growing a screen oxide layer on the sidewalls of said trenches as a protection layer for said sidewalls before carrying out said step of tilt angle body dopant implantation through said sidewalls of said trenches. 
 
     
     
         4 . The method of  claim 1  wherein:
 said step of opening a plurality of trenches in said semiconductor substrate further comprising a step of opening said trenches in a N-type silicon substrate and said step of carrying out said tilt angle body dopant implantation further comprising a step of carrying out tilt angle boron implantation through said sidewalls of said trenches into said N-type silicon substrate to form said body dopant regions surrounding said sidewalls of said trenches. 
 
     
     
         5 . The method of  claim 1  wherein:
 said step of opening a plurality of trenches in said semiconductor substrate further comprising a step of opening said trenches in a N-type silicon substrate and said step of carrying out a vertical source dopant implant further comprising a step of carrying out said source dopant implant of arsenic ions to form said source dopant region below said bottom surface of said trenches 
 
     
     
         6 . The method of  claim 1  further comprising:
 growing a gate oxide layer on said sidewalls and said bottom surface of said trenches and depositing a gate conductive layer into said trenches to form said trenched gates. 
 
     
     
         7 . The method of  claim 1  further comprising:
 growing a gate oxide layer on said sidewalls of said trenches; and 
 forming a bottom gate oxide on said bottom surface of said trenches having a greater thickness than said gate oxide on said sidewalls followed by depositing a gate conductive layer into said trenches to form said trenched gates. 
 
     
     
         8 . The method of  claim 6  further comprising:
 forming body regions and source regions encompassed in said body regions surrounding said trenched gates in said semiconductor substrate and covering semiconductor substrate with an insulation layer followed by opening a plurality of contact trenches through said insulation layer for filling said contact trenches with contact metal plugs with a some of said metal plugs contacting said body regions and source regions and other contact plugs contacting said trenched gates; and 
 depositing a metal layer on top of said insulation layer contacting said metal plugs and patterning said metal layer into a source metal and a gate pad. 
 
     
     
         9 . The method of  claim 6  further comprising:
 forming body regions and source regions encompassed in said body regions surrounding said trenched gates in said semiconductor substrate and covering semiconductor substrate with an insulation layer followed by opening a plurality of contact trenches through said insulation layer for filling said contact trenches with contact metal plugs with a some of said metal plugs contacting said body regions and source regions and other contact plugs contacting said trenched gates; and 
 depositing a low resistance metal layer on top of said insulation layer for enhancing a contact to said metal plugs and forming a metal layer on top of said low resistance metal layer contacting said metal plugs through said low resistance metal layer and patterning said metal layer into a source metal and a gate pad. 
 
     
     
         10 . The method of  claim 6  further comprising:
 implanting a contact dopant region through said contact trenches before depositing said contact metal plugs into said contact trenches to enhance an electrical contact between the source and body regions to the contact metal plugs.