Thermal warp compensation ic package

Abstract

An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art.

1 . A temperature responsive warpage counteracting integrated circuit assembly for use with an integrated circuit package having a connection grid side and a top side, said integrated circuit assembly comprising:
 a first layer of a first material having a first coefficient of temperature expansion and a first and second surface;   a second layer of a second material having a second coefficient of temperature expansion different from said first coefficient of temperature expansion and a first and second surface;   said first surface of said second layer bonded to the second surface of said first layer; and   said second surface of second layer bonded to the top side of said integrated circuit package.   
     
     
         2 . A temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 1  wherein
 said first coefficient of temperature expansion is greater than said second coefficient of temperature expansion. 
 
     
     
         3 . A temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 1  wherein
 said second coefficient of temperature expansion is greater than said first coefficient of temperature expansion. 
 
     
     
         4 . A temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 1  wherein
 said first and second layers have aligned apertures therein. 
 
     
     
         5 . A temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 1  wherein
 said first layer has a planar-convex cross section with the planar portion at said second surface. 
 
     
     
         6 . A temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 1  wherein
 said first layer has a planar-concave cross section with the planar portion at said second surface. 
 
     
     
         7 . A temperature responsive warpage counteracting integrated circuit assembly for use with an integrated circuit package having a connection grid side and a top side, said integrated circuit assembly comprising:
 a layer of a material having a coefficient of temperature expansion that varies from a first value at a first surface to a second value at a second surface;   said second surface of said layer of material bonded to the top side of said integrated circuit package.   
     
     
         8 . A temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 7  wherein
 said first value is greater than said second value. 
 
     
     
         9 . A temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 7  wherein
 said second value is greater than said first value. 
 
     
     
         10 . A temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 7  wherein
 said layer has an aperture therein. 
 
     
     
         11 . A temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 7  wherein
 said layer has planar-convex cross-section with the planar portion at said second surface. 
 
     
     
         12 . A temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 7  wherein
 said layer has planar-concave cross-section with the planar portion at said second surface. 
 
     
     
         13 . A method of manufacture of a temperature responsive warpage counteracting integrated circuit assembly for use with an integrated circuit package having a connection grid side and a top side, said method comprising the steps of:
 providing a first layer of a first material having a first coefficient of temperature expansion and a first and second surface;   providing a second layer of a second material having a second coefficient of temperature expansion different from said first coefficient of temperature expansion and a first and second surface;   bonding said first surface of said second layer to the second surface of said first layer; and   bonding said second surface of second layer to the top side of said integrated circuit package.   
     
     
         14 . A method of manufacture of a temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 13  comprising the additional step of:
 providing that said first coefficient of temperature expansion is greater than said second coefficient of temperature expansion. 
 
     
     
         15 . A method of manufacture of a temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 13  comprising the additional step of:
 providing that said second coefficient of temperature expansion is greater than said first coefficient of temperature expansion. 
 
     
     
         16 . A method of manufacture of a temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 13  comprising the additional step of:
 providing a first aperture in said first layer; and 
 providing a second aperture in said second layer, wherein said second aperture is of generally the same size as said first aperture, and aligned with said first aperture. 
 
     
     
         17 . A method of manufacture of a temperature responsive warpage counteracting integrated circuit assembly for use with an integrated circuit package having a connection grid side and a top side, said method comprising the steps of:
 providing a layer of a material having a coefficient of temperature expansion that varies from a first value at a first surface to a second value at a second surface; and   bonding said second surface of said layer of material to the top side of said integrated circuit package.   
     
     
         18 . A method of manufacture of a temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 17  comprising the additional step of:
 providing that said first value is greater than said second value. 
 
     
     
         19 . A method of manufacture of a temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 17  comprising the additional step of:
 providing that said second value is greater than said first value. 
 
     
     
         20 . A method of manufacture of a temperature responsive warpage counteracting integrated circuit assembly as claimed in  claim 17  comprising the additional step of:
 providing an aperture in said layer.