Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance

Abstract

A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.

1 . A semiconductor device comprising:
 an epitaxy layer formed on a semiconductor substrate;   a device layer formed on the epitaxy layer;   a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor; and   a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor wherein a region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the region of the epitaxy layer is formed of a predetermined thickness ranging from approximately 1 micrometer to approximately 10 micrometers. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the epitaxy layer is an n+ epitaxy layer. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the epitaxy layer has a doping level of about 1×1019 atoms/cm3 or greater. 
     
     
         5 . A semiconductor device comprising:
 an epitaxy layer formed on a semiconductor substrate;   a device layer formed on the epitaxy layer;   a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor; and   an isolating through-silicon via formed within the substrate and surrounding the through-silicon via conductor wherein a region of the epitaxy layer formed between the through-silicon via conductor and the grounded through-silicon via is electrically isolated from any signals applied to the semiconductor device.   
     
     
         6 . The semiconductor device of  claim 5 , wherein the through-silicon via conductor and the isolating through-silicon via are of a same length and width. 
     
     
         7 . The semiconductor device of  claim 5 , wherein the through-silicon via conductor is of a larger length and width than that of the isolating through-silicon via. 
     
     
         8 . The semiconductor device of  claim 5 , wherein the region of the epitaxy layer is formed of a predetermined thickness ranging from approximately 1 micrometer to approximately 10 micrometers. 
     
     
         9 . The semiconductor device of  claim 5 , wherein the epitaxy layer is an n+ epitaxy layer. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the epitaxy layer has a doping level above approximately of about 1×1019 atoms/cm3 or greater. 
     
     
         11 . A semiconductor device comprising:
 a p-doped layer formed on a semiconductor substrate and comprising a higher dopant concentration than that of the semiconductor substrate;   an epitaxy layer formed on the p-doped layer;   a device layer formed on the epitaxy layer; and   a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the p-doped layer is of a predetermined width ranging from approximately 200 nanometer to approximately 2 micrometer and includes a doping concentration of 1×1018 atoms/cm3 or greater. 
     
     
         13 . A semiconductor device comprising:
 an epitaxy layer formed on a semiconductor substrate;   a device layer formed on the epitaxy layer;   a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor; and   a p-doped region implanted beneath the epitaxy layer and adjacent to the through-silicon via conductor and the semiconductor substrate and comprising a higher dopant concentration than that of the semiconductor substrate.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the p-doped region is of a predetermined width ranging from approximately 200 nanometer to approximately 2 micrometers and includes a doping concentration of 1×1018 atoms/cm3 or greater. 
     
     
         15 . A method comprising:
 forming an epitaxy layer on a semiconductor substrate;   forming a trench having a dielectric liner and conductive core within the trench to form a through-silicon via conductor; and   implanting a p-doped region beneath the epitaxy layer and adjacent to the through-silicon via conductor.   
     
     
         16 . The method of  claim 15 , wherein, the p-doped region is formed by performing angled implantation p dopants. 
     
     
         17 . The method of  claim 16 , wherein the p dopants comprise boron (B) or Indium (In). 
     
     
         18 . The method of  claim 16 , wherein the angled implantation is performed after the trench is formed and prior to forming the dielectric liner within the trench. 
     
     
         19 . The method of  claim 16 , wherein the angled implantation is performed after the trench and the dielectric liner are formed. 
     
     
         20 . The method of  claim 16 , wherein the angled implantation is performed from at least four different angles.