Semiconductor Device

Abstract

A vertical transistor of a semiconductor device has a channel area formed in a vertical direction to a semiconductor substrate. After semiconductor poles corresponding to the length of semiconductor channels and gate electrodes surrounding sidewalls of the semiconductor poles are formed, subsequent processes of forming silicon patterns corresponding to junction areas, etc. are performed. The gate electrodes support the semiconductor poles during these subsequent processes. The height of the semiconductor poles corresponding to the length of the channel is increased, yet the semiconductor poles do not collapse or incline since the gate electrodes support the semiconductor poles.

1 . A semiconductor device including a plurality of vertical transistors, the vertical transistors comprising:
 semiconductor poles, each protruding between trenches formed in a semiconductor substrate;   a gate insulating layer formed on circumferences of the semiconductor poles;   gate electrodes formed on circumferences of the gate insulating layer;   silicon patterns formed on tops of the semiconductor poles;   first junction areas formed in trench bottoms of the semiconductor substrate; and   second junction areas formed in the silicon patterns.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising an insulating layer formed over the semiconductor substrate, including spaces between the gate electrodes, and having grooves formed therein, the grooves exposing the semiconductor poles, wherein the silicon patterns are formed in the grooves. 
     
     
         3 . The vertical transistor of  claim 1 , further comprising a first insulating layer formed in spaces between the gate electrodes, wherein the first insulating layer has a height the same as a height of the semiconductor poles. 
     
     
         4 . The vertical transistor of  claim 3 , further comprising a second insulating layer formed on a top surface of the gate electrodes, wherein a top surface of the gate electrodes is lower than top surfaces of the semiconductor poles. 
     
     
         5 . The vertical transistor of  claim 1 , wherein a width of the silicon pattern is identical to or narrower than widths of the semiconductor poles.