US2012074530A1PendingUtilityA1
Interposer including air gap structure, methods of forming the same, semiconductor device including the interposer, and multi-chip package including the interposer
Est. expiryJul 14, 2025(expired)· nominal 20-yr term from priority
H10W 72/536H10W 90/00H10W 20/20H10W 70/60
48
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Claims
Abstract
Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer. The interposer includes a semiconductor substrate including a void, a metal interconnect, provided within the void, thereby forming an air gap insulating the metal interconnect. The metal interconnect may be connected to a contact element, and may be maintained within the air gap using the contact element.
Claims
exact text as granted — not AI-modified1 . An interposer of a semiconductor device comprising:
a semiconductor substrate including a void; and a metal interconnect provided within the void of the semiconductor substrate, thereby forming an insulating air gap to insulate the metal interconnect.
2 . A multi-chip package comprising:
the interposer according to claim 1 ; wherein at least one contact element is formed on one side of the metal interconnect to electrically connect the metal interconnect to a semiconductor integrated circuit, and the semiconductor substrate is attached to the at least one contact element; and a plurality of semiconductor integrated circuits each including a circuit unit having internal elements, and a pad for connecting the circuit unit to the at least one contact element of the interposer, wherein the interposer is bonded to the plurality of semiconductor integrated circuits, and connected to the circuit units of respective semiconductor integrated circuits via the at least one contact element.
3 . The multi-chip package of claim 2 , wherein the metal interconnect is maintained within the air gap using the contact element.
4 . The multi-chip package of claim 2 , wherein each of the semiconductor integrated circuits has no internal metal interconnect for electrical connection of internal elements.
5 . The multi-chip package of claim 2 , wherein an area of the interposer is equal to the sum of areas of the semiconductor integrated circuits.
6 . The multi-chip package of claim 5 , wherein the interposer further comprises an external pad to connect to a printed circuit board, which is connected to the printed circuit board via a bonding element.
7 . The multi-chip package of claim 2 , wherein the area of the interposer is larger than the sum of areas of the semiconductor integrated circuits.
8 . The multi-chip package of claim 7 , wherein the interposer further comprises an external pad to be connected to a printed circuit board, and the external pad is disposed on a portion of the interposer other than an area of the interposer bonded to the semiconductor integrated circuit and is connected to the printed circuit board via a bonding element.
9 . The multi-chip package of claim 2 , wherein the metal interconnect is fabricated using a micro electro mechanical system (MEMS).Join the waitlist — get patent alerts
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