Crack stop structure enhancement of the integrated circuit seal ring

Abstract

An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate.

1 .- 9 . (canceled) 
     
     
         10 . A semiconductor die having a crack stop structure adjacent an active area, the crack stop structure comprising:
 a stacked layer having a plurality of alternating insulating layers and conductive layers; and   an anchor system including at least one anchor having a first portion embedded within a substrate of the semiconductor die and having a second portion coupled to a one of the conductive layers for attaching the stacked layer to the substrate.   
     
     
         11 . The semiconductor die in accordance with  claim 10  wherein the anchor extends through a first insulating layer overlying the substrate. 
     
     
         12 . The semiconductor die in accordance with  claim 11  wherein the anchor comprises metal and extends at least about 10 um below a surface of the substrate. 
     
     
         13 . The semiconductor die in accordance with  claim 12  wherein the anchor comprises copper. 
     
     
         14 . The semiconductor die in accordance with  claim 10  further comprising:
 an isolation layer formed between a surface of the substrate and the anchor. 
 
     
     
         15 . The semiconductor die in accordance with  claim 14  wherein the isolation layer further comprises:
 an isolation insulating layer; and 
 a barrier layer over the isolating insulating layer. 
 
       an isolation layer formed between a surface of the substrate and the anchor. 
     
     
         16 . A semiconductor wafer comprising:
 a substrate; and   a plurality of integrated circuit dies, each integrated circuit die including a die seal ring adjacent an active area, the die seal ring including a crack stop structure, the crack stop structure comprising:
 a stack layer overlying the substrate, and 
 an anchor system coupled to the stack layer and extending from the stack layer to a point below a surface of the substrate. 
   
     
     
         17 . The semiconductor wafer in accordance with  claim 16  wherein the anchor system extends at least about 10 um below the surface of the substrate. 
     
     
         18 . The semiconductor wafer in accordance with  claim 16  wherein the anchor system extends through a first insulating layer overlying the substrate and the anchor system comprises copper. 
     
     
         19 . The semiconductor die in accordance with  claim 16  wherein the anchor system includes a plurality of anchors and the crack stop structure surrounds each of the plurality of integrated circuit dies. 
     
     
         20 . The semiconductor wafer in accordance with  claim 19  further comprising an isolation layer positioned between each of the plurality of anchors and the substrate. 
     
     
         21 . A semiconductor device, comprising:
 a first insulating layer overlying a substrate, the substrate having an active area in which one or more doped regions form at least a part of an active device within the active area;   an anchor extending through the first insulating layer and having at least a portion thereof of a first predetermined material disposed within a crack stop trench within the substrate; and   a stacked layer overlying the first insulating layer, the stacked layer including at least a first conductive layer and a second insulating layer overlying the first conductive layer.   
     
     
         22 . The semiconductor device in accordance with  claim 21  wherein the anchor further comprises a second predetermined material disposed within a via in the first insulating layer, and wherein the first predetermined material and the second predetermined material together form the anchor; and
 wherein the second predetermined material interconnects with the first conductive layer. 
 
     
     
         23 . The semiconductor device in accordance in accordance with  claim 22  wherein the first predetermined material comprises metal. 
     
     
         24 . The semiconductor device in accordance with  claim 22  wherein the first predetermined material comprises copper, the second predetermined material comprises copper and the first conductive layer comprises copper. 
     
     
         25 . The semiconductor device in accordance with  claim 21  further comprising:
 an isolation insulating layer disposed between the substrate and the anchor; and 
 a barrier layer disposed over the isolation insulating layer. 
 
     
     
         26 . The semiconductor device in accordance with  claim 25  wherein the isolation insulating layer comprises oxide and the barrier layer comprises nitride. 
     
     
         27 . The semiconductor device in accordance with  claim 22  further comprising:
 an isolation insulating layer disposed between the substrate and the anchor; 
 a barrier layer disposed over the isolation insulating layer; and 
 wherein the first predetermined material comprises copper, the second predetermined material comprises copper and the first conductive layer comprises metal. 
 
     
     
         28 . The semiconductor device in accordance with  claim 22  wherein the first and second predetermined materials comprise carbon polymer dielectric and the first conductive layer comprises metal. 
     
     
         29 . The semiconductor device in accordance with  claim 22  further comprising:
 a second stacked layer overlying the stacked layer, the second stacked layer including at least a second conductive layer and a third insulating layer overlying the first conductive layer.