Memory device with user configurable density/performance

Abstract

The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of storing a selectable quantity of data bits (e.g., multiple level cells or a single bit per cell). Control circuitry controls the density configuration of read or write operations to the memory blocks in response to a configuration command. In one embodiment, the configuration command is part of the read or write command. In another embodiment, the configuration command is read from a configuration register.

What is claimed is: 
     
         1 . A memory device having selectable density configurations, the device comprising:
 a memory array comprising a plurality of memory cells, each memory cell configured to store a selectable quantity of data bits, the memory array organized into memory blocks;   a configuration register; and   control circuitry, coupled to the memory array, that controls the density configuration in response to a configuration command, wherein each memory block is assigned a plurality of configuration bits of the configuration register such that each memory block is configured to have multiple densities.   
     
     
         2 . The memory device of  claim 1  wherein the plurality of memory cells are floating gate memory cells. 
     
     
         3 . The memory device of  claim 1  wherein the plurality of memory cells are arranged in series strings of memory cells. 
     
     
         4 . The memory device of  claim 1  wherein the configuration register is a non-volatile register. 
     
     
         5 . The memory device of  claim 4  wherein the non-volatile register is a programmable fuse apparatus. 
     
     
         6 . The memory device of  claim 1  wherein the configuration register is a volatile memory array. 
     
     
         7 . The memory device of  claim 1  wherein the configuration register comprises both a non-volatile register and a volatile register. 
     
     
         8 . A NAND flash memory device having selectable density configurations, the device comprising:
 a memory array comprising a plurality of memory cells that are organized into memory blocks, each memory cell configured to store a selectable quantity of data bits;   control circuitry, coupled to the memory array, that determines the density configuration for a memory block in response to a configuration bit; and   a configuration register, coupled to the control circuitry, for storing the configuration bit, wherein each memory block is assigned a plurality of density configuration bits.   
     
     
         9 . The NAND flash memory device of  claim 8  wherein the configuration register is configured to store trimming data, memory block lock data, and record keeping data for the memory device. 
     
     
         10 . A semiconductor, non-volatile memory device having a plurality of selectable density configurations, the device comprising:
 a memory array comprising a plurality of memory cells grouped into memory blocks, each memory cell configured to store a selectable quantity of data bits;   a control bus for receiving density configuration commands that are included in read and write commands; and   control circuitry coupled to the memory array and the control bus and configured to control the density configuration in response to the received density configuration commands and programming of a configuration register, wherein each memory block is assigned a plurality of configuration bits of the configuration register such that each memory block is configured to have multiple densities.   
     
     
         11 . The semiconductor, non-volatile memory device of  claim 10  wherein each bit of the configuration register is assigned to a sub-block level. 
     
     
         12 . The semiconductor, non-volatile memory device of  claim 10  wherein a first state of each bit of the configuration register indicates a first density and a second state of each bit of the configuration register indicates a second density that is greater than the first density. 
     
     
         13 . A method for configuring performance of a memory array, organized as memory blocks, in a memory device, the memory device comprising control circuitry coupled to a configuration register, the method comprising:
 loading configuration data into the configuration register; and   setting a performance configuration for at least a subset of the memory array in response to the configuration data, wherein each memory block is configured to have a plurality of density configurations.   
     
     
         14 . The method of  claim 13  and further comprising the control circuitry receiving a write or read command to determine the density configuration of each memory block. 
     
     
         15 . The method of  claim 13  wherein the control circuitry uses single bit per cell read and write algorithms and multilevel cell read and write algorithms. 
     
     
         16 . The method of  claim 15  wherein the multilevel cell write algorithm stores more than two bits per memory cell. 
     
     
         17 . The method of  claim 13  and further comprising tracking density/performance levels of the memory blocks. 
     
     
         18 . A method for configuring performance of a memory array having a plurality of memory blocks, the method comprising:
 receiving configuration data; and   setting a performance configuration for at least a memory block of the memory array in response to the received configuration data, wherein each memory block is configured to be assigned multiple configuration data.   
     
     
         19 . A method for configuring the density of a memory array, organized as memory blocks, the method comprising:
 receiving a command for initiating one of a read or a write operation on a memory block;   determining if the received command comprises a memory density configuration;   executing one of a single bit per cell read/write routine or a multilevel cell read/write routine on the memory block at the memory density configuration specified in the command; and   storing the memory density configuration from the command in a configuration register, wherein each memory block is configured to have multiple memory density configurations as indicated by the configuration register.   
     
     
         20 . The method of  claim 19  wherein the multilevel cell read/write routine is configured to store a plurality of bits on one memory cell.