Methods of Manufacturing Three-Dimensional Semiconductor Memory Devices

Abstract

Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm 2 to about 10×109 dyne/cm 2 to the substrate and the second material layer applies a stress in a range of about −0.1×109 dyne/cm 2 to about −10×109 dyne/cm 2 to the substrate.

What is claimed is: 
     
         1 . A method of manufacturing a three-dimensional semiconductor device, the method comprising:
 forming a thin film structure on a semiconductor substrate, wherein forming the thin film structure comprises:
 alternately forming a first layer of a first material on the substrate and a second layer of a second material, different from the first material, on the first layer of the first material; and 
 repeating the alternately forming for at least 2n times, where n is an integer more than 2; 
   wherein the first material layer applies a stress in a range of about 0.1×10 9  dyne/cm 2  to about 10×10 9  dyne/cm 2  to the substrate and the second material layer applies a stress in a range of about −0.1×10 9  dyne/cm 2  to about −10×10 9  dyne/cm 2  to the substrate.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming semiconductor patterns that penetrate the thin film structure;   patterning the thin film structure to form a trench that exposes the substrate between the semiconductor patterns;   removing the first material layers exposed to the trench to provide recess regions between the second material layers;   forming a data storage layer that contacts a portion of the semiconductor pattern in each of the recess regions; and   locally forming conductive patterns in the recess regions formed the data storage layer.   
     
     
         3 . The method of  claim 1 , wherein the first material layers are silicon nitride layers deposited using a plasma enhanced chemical vapor deposition technique and the second material layers are silicon oxide layers deposited using a plasma enhanced chemical vapor deposition technique. 
     
     
         4 . The method of  claim 3 , wherein the first and second material layers are formed at a deposition temperature of about 250° C. to about 650° C. 
     
     
         5 . The method of  claim 1 , wherein the forming of the thin film structure comprises forming the first material layers and the second material layers in one chamber. 
     
     
         6 . The method of  claim 1 , wherein the forming of the thin film structure comprises forming first and second material layers on the substrate by alternately using a chamber to form the first material layers and the second material layers. 
     
     
         7 . The method of  claim 1 , wherein forming the thin film structure further comprises adjusting a height difference between a center and an edge of the substrate to be about ±200 μm. 
     
     
         8 . A method of manufacturing a three-dimensional device, the method comprising:
 loading a substrate into a single chamber;   alternately and repeatedly stacking oxide layers and sacrificial layers in the chamber; and   unloading the substrate from the chamber, wherein the oxide layers being deposited using oxygen gas and a source of the oxygen gas comprises nitrous oxide during deposition of the oxide layers.   
     
     
         9 . The method of  claim 8 , wherein the alternately and repeatedly stacking of the oxide layers and the sacrificial layers comprises:
 depositing an oxide layer;   performing a first purging process for purging a first gas mixture used for depositing the oxide layer;   depositing a sacrificial layer; and   performing a second purging process for purging a second gas mixture used for depositing the sacrificial layer;   wherein the depositing of the oxide layer, the first purging process, the depositing of the sacrificial layer, and the second purging process are repeatedly performed in plurality.   
     
     
         10 . The method of  claim 9 , wherein the sacrificial layers are silicon nitride layers and the oxide layers are silicon oxide layers. 
     
     
         11 . The method of  claim 10 , wherein the sacrificial layers are deposited by a first gas mixture including silane and ammonia; and
 the oxide layers are deposited by a second gas mixture including a Tetra-Ethyl-Ortho-Silicate (TEOS) and nitrous oxide.   
     
     
         12 . The method of  claim 11 , wherein each of the first gas mixture and the second gas mixture further comprises carrier gas. 
     
     
         13 . The method of  claim 8 , further comprising:
 forming semiconductor patterns that penetrate the oxide layers and the sacrificial layers;   forming a trench in the alternately and repeatedly stacked sacrificial patterns and oxide patterns by patterning the oxide layers and the sacrificial layers, the semiconductor patterns penetrating the sacrificial patterns and the oxide layer patterns;   forming empty regions between the oxide layer patterns by removing the sacrificial patterns;   conformally forming a multilayer dielectric layer on inner surfaces of the empty region; and   forming gate patterns that fill the empty regions.   
     
     
         14 . The method of  claim 13 :
 wherein the alternately and repeatedly stacked gate patterns and oxide patterns are included in a gate structure; and   wherein the plurality of semiconductor patterns penetrating the gate structure are arranged in one column in one direction.   
     
     
         15 . The method of  claim 13 :
 wherein the alternately and repeatedly stacked gate patterns and oxide patterns are included in a gate structure; and   the plurality of semiconductor patterns penetrating the gate structure are arranged in a zigzag in one direction.