Semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device

Abstract

For constituting a pre-metal interlayer insulating film, such a method is considered as forming a CVD silicon oxide-based insulating film having good filling properties by ozone TEOS, reflowing the film to planarize it, stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and further planarizing by CMP. However, in forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects. In the present invention, in the pre-metal process, after forming the ozone TEOS film over an etch stop film, the ozone TEOS film is once etched back so as to expose the etch stop film over a gate structure, a plasma TEOS film is formed over the remaining ozone TEOS film, and the plasma TEOS film is planarized by CMP.

1 - 24 . (canceled) 
     
     
         25 . A semiconductor integrated circuit device comprising:
 (a) a plurality of MISFET gate structures formed over a first main surface of a semiconductor wafer and including a polysilicon gate electrode;   (b) a source/drain region formed near both sides of the gate structure of the first main surface of the semiconductor wafer;   (c) an etch stop film formed over the first main surface of the semiconductor wafer including the upper surface of the gate structure and the upper surface of the source/drain region;   (d) a first silicon oxide film that is a part of an interlayer insulating film buried between the respective gate structures and is formed by a thermal CVD method, the first silicon oxide film being formed so as to expose the etch stop film formed in the upper surface of the gate structure;   (e) a second silicon oxide film that is a part of the interlayer insulating film and is formed over the etch stop film formed over the first silicon oxide film and the upper surface of the gate structure, which is formed by a plasma CVD method; and   (f) a connection hole in which a plug electrically connecting the source/drain region and a wiring formed over the interlayer insulating film is to be buried.   
     
     
         26 . The semiconductor integrated circuit device according to  claim 25 ,
 wherein an element isolation field insulating film having an STI structure is further formed over the first main surface of the semiconductor wafer, and the etch stop film is formed also including the upper surface of the element isolation field insulating film.   
     
     
         27 . The semiconductor integrated circuit device according to  claim 25 ,
 wherein the connection hole and the source/drain region are electrically connected via the silicide film.   
     
     
         28 . The semiconductor integrated circuit device according to  claim 27 ,
 wherein the silicide film is a nickel silicide film.   
     
     
         29 . The semiconductor integrated circuit device according to  claim 27 ,
 wherein the silicide film is a cobalt silicide film.   
     
     
         30 . The semiconductor integrated circuit device according to  claim 25 ,
 wherein the first silicon oxide film is a film formed by a thermal CVD method using ozone and TEOS at a temperature from 400 to 550° C.   
     
     
         31 . The semiconductor integrated circuit device according to  claim 28 ,
 wherein the first silicon oxide film is a film having not been subjected to an annealing treatment at a temperature over 550° C.   
     
     
         32 . The semiconductor integrated circuit device according to  claim 25 ,
 wherein the hardness of the first silicon oxide film is lower than that of the second silicon oxide film.   
     
     
         33 . A semiconductor integrated circuit device comprising:
 (a) a plurality of MISFET gate structures formed over a first main surface of a semiconductor wafer and including a polysilicon gate electrode;   (b) a source/drain region formed near both sides of the gate structure of the first main surface of the semiconductor wafer;   (c) a silicide film formed on the upper surface of the source/drain region;   (d) an etch stop film formed over the first main surface of the semiconductor wafer including the upper surface of the gate structure and the upper surface of the silicide film of the source/drain region;   (e) a first silicon oxide film that is a part of an interlayer insulating film buried between the respective gate structures and is formed so as not to cover the etch stop film formed in the upper surface of the gate structure;   (f) a second silicon oxide film that is a part of the interlayer insulating film and is formed over the first silicon oxide film and the etch stop film formed in the upper surface of the gate structure; and   (g) a connection hole in which a plug electrically connecting the silicide film formed in the upper surface of the source/drain region and a wiring formed over the interlayer insulating film is buried.   
     
     
         34 . The semiconductor integrated circuit device according to  claim 33 ,
 wherein the silicide film is a nickel silicide film.   
     
     
         35 . The semiconductor integrated circuit device according to  claim 33 ,
 wherein the first silicon oxide film is a film formed by a thermal CVD method using ozone and TEOS at a temperature from 400 to 550° C.   
     
     
         36 . The semiconductor integrated circuit device according to  claim 35 ,
 wherein the first silicon oxide film is a film having not been subjected to an annealing treatment at a temperature over 550° C.   
     
     
         37 . The semiconductor integrated circuit device according to  claim 33 ,
 wherein the hardness of the first silicon oxide film is lower than that of the second silicon oxide film.   
     
     
         38 . A semiconductor integrated circuit device comprising:
 (a) a plurality of MISFET gate structures formed over a first main surface of a semiconductor wafer and including a polysilicon gate electrode;   (b) a source/drain region formed near both sides of the gate structure of the first main surface of the semiconductor wafer;   (c) a silicide film formed in the upper surface of the source/drain region;   (d) an etch stop film formed over the first main surface of the semiconductor wafer including the upper surface of the gate structure and the upper surface of the silicide film;   (e) an interlayer insulating film that is constituted of at least a first silicon oxide film and a second silicon oxide film and is buried between the respective gate structures; and   (g) a connection hole in which a plug electrically connecting the silicide film formed in the upper surface of the source/drain region and a wiring formed over the interlayer insulating film is buried,   wherein the first silicon oxide film is formed so as not to cover the etch stop film formed in the upper surface of the gate structure;   wherein the second silicon oxide film is formed over the first silicon oxide film and the etch stop film formed in the upper surface of the gate structure; and   wherein the hardness of the first silicon oxide film is lower than that of the second silicon oxide film.   
     
     
         39 . The semiconductor integrated circuit device according to  claim 38 ,
 wherein the silicide film is a nickel silicide film.   
     
     
         40 . The semiconductor integrated circuit device according to  claim 38 ,
 wherein the first silicon oxide film is a film formed by a thermal CVD method using ozone and TEOS at a temperature from 400 to 550° C.   
     
     
         41 . The semiconductor integrated circuit device according to  claim 40 ,
 wherein the first silicon oxide film is a film having not been subjected to an annealing treatment at a temperature over 550° C.