Method for forming plating layer of printed circuit board
Abstract
Disclosed herein is a method for forming a plating layer of a printed circuit board. A deviation in plating thickness of a copper plating layer filled in a circuit pattern part and a through-hole part in a SIP product group having a narrow through-hole pitch and a large through-hole volume may be reduced. To this end, there is provided a method for forming a plating layer of a printed circuit board, the method including: processing a though-hole in a copper clad lamination (CCL); forming a seed plating layer in the through hole; applying a resist on the CCL and the seed plating layer and exposing and developing the resist; forming a primary plating layer on the seed plating layer; forming a copper plating layer on the primary plating layer; and removing the resist remaining on the primary plating layer and the seed plating layer to thereby form patterns.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for forming a plating layer of a printed circuit board, the method comprising:
processing a though-hole in a copper clad lamination (CCL); forming a seed plating layer in the through hole; applying a resist on the CCL and the seed plating layer and exposing and developing the resist; forming a primary plating layer on the seed plating layer; forming a copper plating layer on the primary plating layer; and removing the resist remaining on the primary plating layer and the seed plating layer to thereby form patterns.
2 . The method according to claim 1 , wherein the through-hole is formed by a mechanical method and a chemical method.
3 . The method according to claim 2 , wherein the mechanical method is a drill and laser processing method, and the chemical method is an etching method.
4 . The method according to claim 1 , wherein the primary plating layer has a thickness of 3 to 5 μm.
5 . The method according to claim 4 , wherein the primary plating layer is plated with a low current having a current density of 0.5 A/dm 2 to 1.0 A/dm 2 or less.
6 . The method according to claim 1 , wherein the copper plating layer is formed on the primary plating layer so as to have a thickness of 20 to 25 μm.
7 . The method according to claim 6 , wherein the copper plating layer is plated with a high current having a current density of 1.5 A/dm 2 to 2.0 A/dm 2 or more.Join the waitlist — get patent alerts
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