Semiconductor devices having dielectric gaps

Abstract

A method of fabricating a semiconductor device, can be provided by forming first and second gate patterns on a semiconductor substrate. First and second insulating spacers can be formed on first and second sidewalls of the first and second gate patterns, respectively. A capping insulation can be formed on an entire surface of the semiconductor substrate including on the first and second insulating spacers. The first insulating spacers can be removed to form an air gap between the first and second gate patterns. Related devices are also disclosed.

1 .- 6 . (canceled) 
     
     
         7 . A semiconductor device comprising:
 a device isolation layer on a semiconductor substrate to define a plurality of main active regions;   first and second gate patterns crossing over the main active regions and the device isolation layer therebetween;   a common source line in the semiconductor substrate between the first and second gate patterns;   a capping insulation layer covering an air gap between the first and second gate patterns;   a plurality of first drain regions in the main active regions located immediately adjacent to the first gate pattern and located distal from the second gate pattern, respectively; and   a plurality of second drain regions in the main active regions located immediately adjacent to the second gate pattern and located distal from the first gate pattern, respectively.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the first gate pattern comprises a first sidewall adjacent to the common source line and a second sidewall immediately adjacent to the first drain regions and the second gate pattern comprises a first sidewall adjacent to the common source line and a second sidewall adjacent to the second drain regions. 
     
     
         9 . The semiconductor device of  claim 8 , further comprising:
 an insulating spacer on the second sidewalls of the first and second gate patterns, wherein the capping insulation layer comprises a material layer having an etch selectivity with respect to the insulating spacer.   
     
     
         10 . The semiconductor device of  claim 7 , wherein the capping insulation layer extends to cover the first and second drain regions, and the capping insulation layer provides no air gap between the capping insulation layer and the drain regions. 
     
     
         11 . The semiconductor device of  claim 7 , further comprising:
 an interlayer insulation layer on the capping insulation layer; and   bit lines on the interlayer insulation layer,   wherein each of the bit lines is electrically connected to the first and second drain regions formed in one of the main active regions.   
     
     
         12 . The semiconductor device of  claim 7 , further comprising at least one dummy active region defined by the device isolation layer and disposed adjacent to the main active regions,
 wherein the first and second gate patterns extend to cross over the dummy active region.   
     
     
         13 . The semiconductor device of  claim 12 , wherein a first interval between the first and second gate patterns crossing over the main active regions is less than a second interval between the first and second gate patterns crossing over the dummy active region. 
     
     
         14 . The semiconductor device of  claim 13 , further comprising:
 an interlayer insulation layer on the capping insulation layer; and   at least one source interconnection disposed on the interlayer insulation layer,   wherein the source interconnection is electrically connected to the common source line.   
     
     
         15 . A non-volatile semiconductor memory device comprising:
 immediately adjacent floating gates spaced apart by a gap on a semiconductor substrate in a main memory region of the device;   a capping insulating layer, above the substrate, bridging the gap; and   a common source line in the semiconductor substrate shared by the immediately adjacent floating gates.   
     
     
         16 . The device according to  claim 15  wherein the capping insulating layer extends over the immediately adjacent floating gates and onto sidewalls thereof in the main memory region of the device over immediately adjacent drain regions in the semiconductor substrate. 
     
     
         17 . The device according to  claim 16  further comprising:
 a bit line in the main memory region of the device penetrating the capping insulating layer to electrically connect to one of the immediately adjacent drain regions. 
 
     
     
         18 . The device according to  claim 17  wherein the gap comprises a first distance, the device further comprising:
 a dummy floating gate, in a dummy region of the device, spaced apart from a closest one of the immediately adjacent floating gates by a second distance that is greater than the first distance. 
 
     
     
         19 . The device according to  claim 18  wherein the second distance is greater than the first distance. 
     
     
         20 . The device according to  claim 18  wherein the second distance between the dummy floating gate and the closest one of the immediately adjacent floating gates is free of the gap.