Data output circuit in a semiconductor memory apparatus

Abstract

A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

1 - 22 . (canceled) 
     
     
         23 . A data output circuit comprising:
 a driver including a main driver configured to drive an output node in response to an input signal and a sub driver configured to additionally drive the output node in response to an inverted signal obtained by inverting a voltage level on the output node; and   an output unit coupled to the output node to generate an output data.   
     
     
         24 . The data output circuit of  claim 23 , wherein the sub driver includes:
 a switching unit configured to generate the inverted signal in response to the input signal; and   a driving unit configured to drive the output node in response to the inverted signal.   
     
     
         25 . The data output circuit of  claim 24 , wherein the switching unit includes a tri-state inverter which is configured to generate the inverted signal. 
     
     
         26 . The data output circuit of  claim 23 , wherein the sub driver drives the output node when the voltage level of the output node transits. 
     
     
         27 . The data output circuit of  claim 23 , wherein if the input signal is a logic high state, the main driver and the sub driver drive the output node to logic high state. 
     
     
         28 . The data output circuit of  claim 23 , wherein if the input signal is a logic low state, the main driver and the sub driver drive the output node to logic low state. 
     
     
         29 . The data output circuit of  claim 23 , wherein the output unit includes a pad outputting the output data to an external circuit. 
     
     
         30 . The data output circuit of  claim 23 , wherein the output unit includes a buffer unit buffering the output data. 
     
     
         31 . The data output circuit comprising:
 a pre-driving unit configured to generate an input signal in response to an input data;   a driver including a main driver configured to drive an output node in response to the input signal and a sub driver configured to additionally drive the output node in response to an inverted signal obtained by inverting a voltage level on the output node; and   an output unit coupled to the output node to generate an output data.   
     
     
         32 . The data output circuit of  claim 31 , wherein the sub driver includes:
 a switching unit configured to generate the inverted signal in response to the input signal; and   a driving unit configured to drive the output node in response to the inverted signal.   
     
     
         33 . The data output circuit of  claim 32 , wherein the switching unit includes a tri-state inverter which is configured to generate the inverted signal. 
     
     
         34 . The data output circuit of  claim 31 , wherein the pre-driving unit generates a logic high signal or a logic low signal in response to the input data. 
     
     
         35 . The data output circuit of  claim 34 , wherein the main driver and the sub driver drive the output node to logic high state in response to the logic high signal. 
     
     
         36 . The data output circuit of  claim 35 , wherein the main driver includes a plurality of PMOS transistors each of which has a gate receiving the logic high signal, a source receiving an external power supply voltage, and a drain coupled to the output node. 
     
     
         37 . The data output circuit of  claim 35 , wherein the sub driver includes a PMOS transistor having a gate receiving the inverted signal, a source receiving an external power supply voltage, and a drain coupled to the output node. 
     
     
         38 . The data output circuit of  claim 34 , wherein the main driver and sub driver drive the output node to logic low state in response to the logic low signal. 
     
     
         39 . The data output circuit of  claim 38 , wherein the main driver includes a plurality of NMOS transistors each of which has a gate receiving the logic low signal, a source receiving a ground voltage, and a drain coupled to the output node. 
     
     
         40 . The data output circuit of  claim 38 , wherein the sub driver includes a NMOS transistor having a gate receiving the inverted signal, a source receiving a ground voltage, and a drain coupled to the output node. 
     
     
         41 . The data output circuit of  claim 31 , wherein the sub driver drives the output node when the voltage level of the output node transits. 
     
     
         42 . The data output circuit of  claim 31 , wherein the output unit includes a pad outputting the output data to an external circuit. 
     
     
         43 . The data output circuit of  claim 31 , wherein the output unit includes a buffer unit buffering the output data. 
     
     
         44 . A data output circuit comprising:
 a pre-driving unit configured to generate a pull-up signal in response to an input data; and   a pull-up driver including a first main driver configured to drive a first node to logic high state in response to the pull-up signal and a first sub driver configured to additionally drive the first node to logic high state in response to a first inverted signal obtained by inverting a voltage level on the first node.   
     
     
         45 . The data output circuit of  claim 44 , wherein the first sub driver includes:
 a first switching unit configured to generate the first inverted signal in response to the pull-up signal; and   a first driving unit configured to drive the first node to logic high state in response to the first inverted signal.   
     
     
         46 . The data output circuit of  claim 45 , wherein the first switching unit includes a first tri-state inverter which is configured to generate the first inverted signal. 
     
     
         47 . The data output circuit of  claim 46 , wherein the first tri-state inverter is turned on by the pull-up signal. 
     
     
         48 . The data output circuit of  claim 45 , wherein the first driving unit includes a PMOS transistor having a gate receiving the first inverted signal, a source receiving an external power supply voltage, and a drain coupled to the first node. 
     
     
         49 . The data output circuit of  claim 44 , wherein the first main driver includes a plurality of PMOS transistors each of which has a gate receiving the pull-up signal, a source receiving an external power supply voltage, and a drain coupled to the first node. 
     
     
         50 . The data output circuit of  claim 44 , wherein the pre-driving unit is configured to generate a pull-down signal in response to the input data. 
     
     
         51 . The data output circuit of  claim 50 , further comprising:
 a pull-down driver including a second main driver configured to drive a second node to logic low state in response to the pull-down signal and a second sub driver configured to additionally drive the second node to logic low state in response to a second inverted signal obtained by inverting a voltage level on the second node.   
     
     
         52 . The data output circuit of  claim 51 , wherein the second sub driver includes:
 a second switching unit configured to generate the second inverted signal in response to the pull-down signal; and   a second driving unit configured to drive the second node to logic low state in response to the second inverted signal.   
     
     
         53 . The data output circuit of  claim 52 , wherein the second switching unit includes a second tri-state inverter which is configured to generate the second inverted signal. 
     
     
         54 . The data output circuit of  claim 53 , wherein the second tri-state inverter is turned on by the pull-down signal. 
     
     
         55 . The data output circuit of  claim 52 , wherein the second driving unit includes a NMOS transistor having a gate receiving the second inverted signal, a source receiving a ground voltage, and a drain coupled to the second node. 
     
     
         56 . The data output circuit of  claim 51 , wherein the second main driver includes a plurality of NMOS transistors each of which has a gate receiving the pull-down signal, a source receiving a ground voltage, and a drain coupled to the second node. 
     
     
         57 . The data output circuit of  claim 51 , wherein the first sub driver drives the first node when the voltage level of the first node transitions, and
 wherein the second sub driver drives the second node when the voltage level of the second node transitions.   
     
     
         58 . The data output circuit of  claim 51 , further comprising:
 an output unit coupled to the first node and the second node to generate an output data.   
     
     
         59 . The data output circuit of  claim 50 , wherein the pre-driving unit includes:
 a first pre-driver configured to generate the pull-up signal in response to the input data; and   a second pre-driver configured to generate the pull-down signal in response to the input data.