Thin film transistor, method of fabricating thin film transistor and pixel structure

Abstract

A method of fabricating a TFT includes providing a substrate where a gate, an insulating layer, and a channel layer are formed. A conductive layer is formed on the substrate to cover the channel layer and the insulating layer. A photoresist layer is formed on the conductive layer. A photo mask is placed above the photoresist layer and has a data line pattern, a source pattern, and a drain pattern. A first width (W 1 ) between the source pattern and the drain pattern and a second width (W 2 ) of the data line pattern satisfy the following: if W 1 −1(um), then W 2 +a(um), and 0.3<a<0.7. An exposing process is performed by using the photo mask, and a development process is performed to pattern the photoresist layer. The conductive layer is patterned by using the photoresist layer as an etching mask to form a source, a drain, and a data line.

What is claimed is: 
     
         1 . A method of fabricating a thin film transistor, comprising:
 providing a substrate, a gate, an insulating layer, and a channel layer being formed on the substrate;   forming a conductive layer on the substrate, the conductive layer covering the channel layer and the insulating layer;   forming a photoresist layer on the conductive layer;   placing a photo mask above the photoresist layer, the photo mask having a data line pattern, a source pattern, and a drain pattern, a first width (W 1 ) existing between the source pattern and the drain pattern, the data line pattern having a second width (W 2 ), wherein the first width (W 1 ) and the second width (W 2 ) satisfy the following:   if W 1 −1(um), then W 2 +a(um), and 0.3<a<0.7;   performing an exposing process with use of the photo mask and performing a development process to pattern the photoresist layer; and   patterning the conductive layer with use of the photoresist layer as an etching mask to form a source, a drain, and a data line.   
     
     
         2 . The method as claimed in  claim 1 , wherein a thickness of the photoresist layer corresponding to the data line pattern of the photo mask is greater than a thickness of the photoresist layer corresponding to the source pattern and the drain pattern of the photo mask. 
     
     
         3 . The method as claimed in  claim 2 , wherein the thickness of the photoresist layer corresponding to the data line pattern of the photo mask differs from the thickness of the photoresist layer corresponding to the source pattern and the drain pattern of the photo mask by about 4900 angstroms˜about 6200 angstroms. 
     
     
         4 . The method as claimed in  claim 1 , wherein energy of the exposing process is approximately 23 mj/cm 2 ˜26 mj/cm 2 . 
     
     
         5 . A thin film transistor electrically connected to a scan line and comprising:
 a gate, a channel layer, a source, and a drain,   wherein the source and the drain extend away from the scan line, a first distance exists between the source and the drain and corresponds to an area above the channel layer, a second distance exists between the source and the drain and corresponds to an area above the scan line, and the second distance is greater than the first distance, such that the source and the drain respectively have a deflection portion,   the scan line and the deflection portions of the source and the drain being overlapped by about 0 um˜about 1 um.   
     
     
         6 . The thin film transistor as claimed in  claim 5 , wherein the scan line and the deflection portions of the source and the drain are overlapped by about 0 um˜about 0.5 um. 
     
     
         7 . The thin film transistor as claimed in  claim 5 , wherein the deflection portions of the source and the drain have an extending direction, the scan line has an extending direction, and an acute angle (α) is between the extending direction of the deflection portions of the source and the drain and the extending direction of the scan line. 
     
     
         8 . The thin film transistor as claimed in  claim 7 , wherein 0°<α≦45°. 
     
     
         9 . A thin film transistor electrically connected to a scan line and comprising:
 a gate, a channel layer, a source, and a drain,   wherein the source and the drain extend away from the scan line, a first distance exists between the source and the drain and corresponds to an area above the channel layer, a second distance exists between the source and the drain and corresponds to an area above the scan line, and the second distance is greater than the first distance, such that the source and the drain respectively have a deflection portion,   the deflection portions of the source and the drain having an extending direction, the scan line having an extending direction, an acute angle (α) being between the extending direction of the deflection portions of the source and the drain and the extending direction of the scan line.   
     
     
         10 . The thin film transistor as claimed in  claim 9 , wherein 0°<α≦45°. 
     
     
         11 . A pixel structure comprising:
 a data line;   a first scan line not parallel to the data line;   a first thin film transistor and a second thin film transistor, the first and second thin film transistors being disposed on the first scan line and electrically connected to the first scan line and the data line, the first thin film transistor having a first gate, a first channel layer, a first source, and a first drain, the second thin film transistor having a second gate, a second channel layer, a second source, and a second drain, wherein the first source is electrically connected to the data line, and the second drain is connected to the first source;   a second scan line parallel to the first scan line;   a third thin film transistor disposed on the second scan line and electrically connected to the second scan line, the third thin film transistor having a third gate, a third channel layer, a third source, and a third drain, the third source being connected to the second source;   a main pixel electrode electrically connected to the first drain of the first thin film transistor;   a sub-pixel electrode electrically connected to the third source of the third thin film transistor,   wherein the third source and the third drain extend away from the second scan line, a first distance exists between the third source and the third drain and corresponds to an area above the third channel layer, a second distance exists between the third source and the third drain and corresponds to an area above the second scan line, and the second distance is greater than the first distance, such that the third source and the third drain respectively have a deflection portion,   the second scan line and the deflection portions of the third source and the third drain being overlapped by about 0 um˜about 1 um.   
     
     
         12 . The pixel structure as claimed in  claim 11 , wherein the second scan line and the deflection portions of the third source and the third drain are overlapped by about 0 um˜about 0.5 um. 
     
     
         13 . The pixel structure as claimed in  claim 11 , wherein the deflection portions of the third source and the third drain have an extending direction, the second scan line has an extending direction, and an acute angle (α) is between the extending direction of the deflection portions of the third source and the third drain and the extending direction of the second scan line. 
     
     
         14 . The pixel structure as claimed in  claim 13 , wherein 0°<α≦45°. 
     
     
         15 . A pixel structure comprising:
 a data line;   a first scan line not parallel to the data line;   a first thin film transistor and a second thin film transistor, the first and second thin film transistors being disposed on the first scan line and electrically connected to the first scan line and the data line, the first thin film transistor having a first gate, a first channel layer, a first source, and a first drain, the second thin film transistor having a second gate, a second channel layer, a second source, and a second drain, wherein the first source is electrically connected to the data line, and the second drain is connected to the first source;   a second scan line parallel to the first scan line;   a third thin film transistor disposed on the second scan line and electrically connected to the second scan line, the third thin film transistor having a third gate, a third channel layer, a third source, and a third drain, the third source being connected to the second source;   a main pixel electrode electrically connected to the first drain of the first thin film transistor;   a sub-pixel electrode electrically connected to the third source of the third thin film transistor,   wherein the third source and the third drain extend away from the second scan line, a first distance exists between the third source and the third drain and corresponds to an area above the third channel layer, a second distance exists between the third source and the third drain and corresponds to an area above the second scan line, and the second distance is greater than the first distance, such that the third source and the third drain respectively have a deflection portion,   the deflection portions of the third source and the third drain having an extending direction, the second scan line having an extending direction, an acute angle (α) being between the extending direction of the deflection portions of the third source and the third drain and the extending direction of the second scan line.   
     
     
         16 . The pixel structure as claimed in  claim 15 , wherein 0°<α≦45°.