Embedded-dram processing apparatus and methods

Abstract

An embedded-DRAM processor architecture includes a DRAM array, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-address registers and is responsive to commands to activate and deactivate DRAM rows and to control the movement of data throughout the system. A pipelined data assembly approach allowing the functional units to perform register-to-register operations, and allowing the data assembly unit to perform all load/store operations using wide data busses. Data masking and switching hardware allows individual data words or groups of words to be transferred between the registers and memory. Other aspects of the disclosure include a memory and logic structure and an associated method to extract data blocks from memory to accelerate, for example, operations related to image compression and decompression.

1 .- 26 . (canceled) 
     
     
         27 . An embedded dynamic random access memory (DRAM) processor comprising:
 a DRAM array integrated on-chip with said processor comprising a plurality of random access memory cells arranged in rows and columns;   at least two register files, said register files each comprising a plurality of individually accessible registers, said registers being loadable in parallel via a parallel access port;   a data path comprising a mask and switch unit responsive to a set of program-controlled permutation bits, said permutation bits indicative of a permutation pattern used to rearrange relative positions of data bits as said data bits pass through said unit, said data path being capable of coupling at least a portion of a selected row of said DRAM array to the parallel access port corresponding to one of said register files;   a plurality of functional units coupled to said register files and being able to individually access ones of said registers in response to a first set of instructions drawn from an instruction stream; and   a data assembly unit responsive to a second set of instructions drawn from said instruction stream;   wherein said functional units collectively execute said first set of instructions, and in parallel with the functional units, said data assembly unit executes said second set of instructions, and said data assembly unit is operative to cause data to be moved into and out of said register files in support of said functional units.   
     
     
         28 . The embedded-DRAM processor of  claim 27 , wherein said registers are individually addressable via a second port. 
     
     
         29 . The embedded-DRAM processor of  claim 28 , further comprising at least one register file which is inactive for at least a period of time, whereby said data assembly unit further comprises an inter-register move unit that causes data to be moved between selected registers in said at least one register file in response to an instruction from said second instruction set. 
     
     
         30 . The embedded-DRAM processor of  claim 28 , wherein:
 said at least two register files comprises at least first and second register files, and   said second set of instructions comprises a command to cause said first register file to toggle from an inactive state to an active state, and to cause said second register file to toggle from said inactive state to said active state.   
     
     
         31 . The embedded-DRAM processor of  claim 30 , wherein registers of the register file in the active state comprise architectural registers accessible to said functional units, and said register file in said inactive state is not accessible to said functional units, but is accessible to said data assembly unit. 
     
     
         32 . The embedded-DRAM processor of  claim 31 , whereby said second set of instructions comprises a command to cause at least one register file to toggle between said inactive state and said active state. 
     
     
         33 . The embedded-DRAM processor of  claim 31 , wherein said second set of instructions comprises a command to cause said first register file to toggle from said inactive state to said active state, and to cause said second register file to toggle from said inactive state to said active state. 
     
     
         34 . The embedded-DRAM processor of  claim 31 , wherein said data assembly unit further comprises an inter-register move unit that causes data to be moved between selected registers in one or more inactive register files in response to an instruction from said second instruction set. 
     
     
         35 . A data processing apparatus, comprising:
 an embedded dynamic random access memory (DRAM) array comprising a plurality of memory cells arranged in rows and columns;   at least two register files, each comprising a plurality of individually accessible registers, said registers being loadable in parallel via a parallel access port;   a data path capable of coupling at least a portion of a selected row of said DRAM array to the parallel access port corresponding to one of said register files;   a plurality of functional units coupled to said register files, at least two of said functional units being able to individually access in parallel ones of said registers in response to parallel execution of respective first and second instructions of a first set of instructions drawn from an instruction stream; and   a data assembly unit responsive to a second set of instructions drawn from said instruction stream;   wherein said functional units are configured to collectively execute said first set of instructions, and said data assembly unit is configured to execute, in parallel with said functional units, said second set of instructions; and   wherein said data assembly unit is operative to cause data to be moved into and out of said register files in support of said functional units.   
     
     
         36 . The data processing apparatus of  claim 35 , wherein said second set of instructions comprises:
 a command to cause content of a selected register file to be loaded in parallel from a selected DRAM row; and   a command to cause the contents of said selected register file to be stored in parallel to a selected DRAM row.   
     
     
         37 . The data processing apparatus of  claim 35 , wherein said second set of instructions comprises a command to cause a selected DRAM row to be pre-charged. 
     
     
         38 . The data processing apparatus of  claim 35 , whereby instructions in said first set of instructions implement a register-to-register based programming model executed by said functional units, and instructions in said second set of instructions that implement look-ahead oriented data move operations to cause data used by the functional units to be available when needed. 
     
     
         39 . The data processing apparatus of  claim 38 , wherein:
 said second instruction set is used to implement a first caching scheme, and   said at least two register files act as a cache, and said second set of instructions is executed in lieu of a second caching scheme that maintains most recently used data and enforces a set associative or a direct-mapped caching policy.   
     
     
         40 . The data processing apparatus of  claim 35 , wherein the data processing apparatus is configured for processing multimedia data. 
     
     
         41 . The data processing apparatus of  claim 35 , wherein the data processing apparatus is configured for processing cellular communications data. 
     
     
         42 . The data processing apparatus of  claim 35 , wherein the data processing apparatus comprises a computer graphics processor apparatus. 
     
     
         43 . The data processing apparatus of  claim 35 , further comprising:
 an instruction register configured to receive instructions from said instruction stream, said instruction register operative to hold an instruction to be executed by said data assembly unit; and   a local program memory coupled to said instruction register;   wherein said data assembly unit receives an instruction from said instruction stream that causes a separate control thread of instructions to be accessed from said local program memory and executed by said data assembly unit.   
     
     
         44 . The data processing apparatus of  claim 35 , wherein said data assembly unit further comprises an instruction register coupled to receive instructions fetched by a second pre-fetch unit which fetches instructions for said data assembly unit from a local store. 
     
     
         45 . The data processing apparatus of  claim 35 , further comprising:
 a plurality of DRAM banks, wherein each DRAM bank comprises a plurality of DRAM arrays; and   a row control circuit for selecting in response to a row address, a row of data words in one of said DRAM banks.   
     
     
         46 . An embedded dynamic random access memory (DRAM) processing apparatus, comprising:
 an embedded DRAM array comprising a plurality of random access memory cells arranged in rows and columns;   an embedded row address register that holds a pointer that points to a row of the embedded DRAM array;   an interconnect network comprising embedded first and second register files, each of said register files capable of loading or storing an entire row of the DRAM array in response to a single latch signal;   a pre-fetch buffer coupled to an output of the interconnection network and configured to fed an instruction stream to a branch instruction cache; and   at least one branch functional unit, operably coupled to said branch instruction cache, and configured to execute branch instructions.   
     
     
         47 . The embedded DRAM processing apparatus of  claim 46 , wherein said branch functional unit is configured to provide branch evaluation and target address data to said branch instruction cache. 
     
     
         48 . The embedded DRAM processing apparatus of  claim 46 , wherein said pre-fetch buffer is configured to provide a tag to said branch instruction cache indicating a program execution branch. 
     
     
         49 . The embedded DRAM processing apparatus of  claim 48 , wherein said branch instruction cache is configured to cache a plurality of program instructions from said instruction stream based at least in part on said tag. 
     
     
         50 . The embedded DRAM processing apparatus of  claim 49 , wherein:
 said tag comprises an indication of a first program branch;   said plurality of program instructions comprises at least a portion of instructions corresponding to said first program branch; and   said plurality of instructions is fetched by said functional unit from said branch instruction cache upon receiving a subsequent tag indicative of said first program branch.