US2012034779A1PendingUtilityA1

Apparatus for manufacturing a semiconductor device

Assignee: SHIMURA SATORUPriority: Jul 2, 2004Filed: Oct 19, 2011Published: Feb 9, 2012
Est. expiryJul 2, 2024(expired)· nominal 20-yr term from priority
H10P 95/08H10P 72/0468H10P 72/0458H10P 72/0454H10P 70/234H10P 50/287H10P 50/283H10W 20/096H10W 20/087H10W 20/085H10W 20/081H10W 20/076
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Claims

Abstract

In a semiconductor device manufacturing method, an etching mask ( 75 b ) having a predetermined opening pattern is formed on an etching target film ( 74 ) disposed on a target object. Then, an etching process is performed on the etching target film ( 74 ) through the opening pattern of the etching mask ( 75 b ) within a first process chamber, thereby forming a groove or hole ( 78 a ) in the etching target film. Then, the target object treated by the etching process is transferred from the first process chamber to a second process chamber, within a vacuum atmosphere. Then, a silylation process is performed on a side surface of the groove or hole ( 78 a ), which is an exposed portion of the etching target film ( 74 ), within the second process chamber.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device manufacturing method comprising:
 performing an etching process on an etching target film formed on a substrate, thereby forming a groove or hole in the etching target film, while using an etching mask having a circuit pattern disposed on the etching target film;   performing an ashing process on the etching mask, thereby removing the etching mask, after the etching process; and   performing a silylation process on an inner surface of the groove or hole after the ashing process.   
     
     
         2 . The method according to  claim 1 , wherein the ashing process is arranged to use an ashing gas comprising a gas selected from the group consisting of O 2  and CO 2 . 
     
     
         3 . The method according to  claim 1 , wherein the etching target film comprises an organic low dielectric film. 
     
     
         4 . The method according to  claim 3 , wherein the organic low dielectric film is a Porous MSQ film. 
     
     
         5 . The method according to  claim 3 , wherein the etching mask comprises an SiCN film, an anti-reflective coating, and a resist film disposed in this order from below on the organic low dielectric film. 
     
     
         6 . The method according to  claim 1 , wherein the silylation process is arranged to use a gas selected from the group consisting of TMDS (1,1,3,3-Tetramethyldisilazane) and TMSDMA (Dimethylaminotrimethylsilane). 
     
     
         7 . The method according to  claim 1 , wherein the etching process, the ashing process, and the silylation process are sequentially performed in a vacuum state. 
     
     
         8 . The method according to  claim 1 , wherein the etching process and the ashing process are performed inside the same process chamber. 
     
     
         9 . The method according to  claim 1 , wherein the etching process, the ashing process, and the silylation process are performed inside the same process chamber.

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