Semiconductor device

Abstract

To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

1 - 19 . (canceled) 
     
     
         20 . A method of manufacturing a semiconductor device, comprising the steps of:
 (a) providing a lead frame including a chip mounting portion, a source lead, and a gate lead, wherein each of the chip mounting portion, the source lead, and the gate lead are electrically separated;   (b) providing a semiconductor chip including a power MOSFET, an obverse surface, and a reverse surface opposite the obverse surface,   wherein a source electrode pad and a gate electrode pad are formed on the obverse surface, and   wherein a drain electrode is formed on the reverse surface;   (c) mounting the semiconductor chip over a top surface of the chip mounting portion and connecting the drain electrode of the semiconductor chip and the chip mounting portion electrically;   (d) connecting the metal ribbon to the source electrode pad of the semiconductor chip and to the first lead of the lead frame electrically using a first bonding tool; and   (e) after the step (d), connecting the metal wire to the gate electrode pad of the semiconductor chip and to the first lead of the lead frame electrically using a second bonding tool.   
     
     
         21 . The method of manufacturing a semiconductor device according to  claim 20 ,
 wherein in the step (d), said connection of the metal ribbon and the source electrode pad of the semiconductor chip is made two or more times.   
     
     
         22 . The method of manufacturing a semiconductor device according to  claim 21 ,
 wherein a plurality of connecting portions of the metal ribbon and the source electrode pad of the semiconductor chip is formed over the source electrode pad of the semiconductor chip.   
     
     
         23 . The method of manufacturing a semiconductor device according to  claim 22 ,
 wherein a width of each of the plurality of connecting portion is substantially the same.   
     
     
         24 . The method of manufacturing a semiconductor device according to  claim 20 ,
 wherein a vibration energy of the first bonding tool is larger than a vibration energy of the second bonding tool.   
     
     
         25 . The method of manufacturing a semiconductor device according to  claim 20 ,
 wherein the semiconductor chip is mounted over the top surface of the chip mounting portion via Ag paste.   
     
     
         26 . The method of manufacturing a semiconductor device according to  claim 20 , further comprising the steps of:
 (f) sealing the semiconductor chip, a part of the chip mounting portion, a part of the source lead, a part of the gate lead, the metal ribbon, and the metal wire using a sealing body; and   (g) cutting each of said parts of the source and gate leads from the lead frame.   
     
     
         27 . The method of manufacturing a semiconductor device according to  claim 26 ,
 wherein the chip mounting portion is sealed such that a bottom surface opposite the top surface of the chip mounting portion is exposed from the sealing body.   
     
     
         28 . The method of manufacturing a semiconductor device according to  claim 20 ,
 wherein the lead frame has a drain lead which is coupled the chip mounting portion, and   wherein the drain electrode of the semiconductor chip is connected to the drain lead electrically.   
     
     
         29 . The method of manufacturing a semiconductor device according to  claim 20 ,
 wherein an area of the source pad is larger than an area of the gate pad.