Dynamic random access memory having junction field effect transistor cell access device

Abstract

A method of fabricating a dynamic random access memory (DRAM) can include depositing a semiconductor electrode layer in contact with a surface of a semiconductor substrate; patterning the electrode layer to form a plurality of access junction field effect transistor (JFET) gate electrodes and a plurality of sense amplifier bipolar junction transistor (BJT) electrodes; and forming a charge storage structure coupled to a source of each access JFET.

1 . A method of fabricating a dynamic random access memory (DRAM), comprising the steps of:
 depositing a semiconductor electrode layer in contact with a surface of a semiconductor substrate;   patterning the electrode layer to form a plurality of access junction field effect transistor (JFET) gate electrodes and a plurality of sense amplifier bipolar junction transistor (BJT) electrodes; and   forming a charge storage structure coupled to a source of each access JFET.   
     
     
         2 . The method of  claim 1 , wherein:
 forming the charge storage structures includes forming capacitors having a first plate separated from a second plate by a capacitor dielectric.   
     
     
         3 . The method of  claim 2 , wherein:
 forming each capacitor first plate includes   depositing an interlayer dielectric (ILD),   forming a capacitor contact hole through the ILD to a source of the corresponding access JFET, and   forming the first plate that is conductively connected to the source of the corresponding access JFET.   
     
     
         4 . The method of  claim 2 , further including:
 depositing an interlayer dielectric (ILD),   forming sense input contact holes through the ILD to the sense amplifier BJT electrodes, and   forming a conductive interconnect layer that has sections that are conductively connected to the sense amplifier BJT electrodes.   
     
     
         5 . The method of  claim 4 , wherein:
 the conductive interconnect layer is formed over the capacitor second plate.   
     
     
         6 . The method of  claim 4 , wherein:
 the conductive interconnect layer is formed below the capacitor second plate.   
     
     
         7 . The method of  claim 1 , further including:
 patterning the electrode layer also forms access JFET source electrodes, JFET drain electrodes, and forms sense amplifier BJT emitter and base electrodes;   forming link diffusion regions for the access JFETs in the semiconductor substrate that are self-aligned to the JFET source, drain and gate electrodes, the link regions being doped to the same conductivity type as source and drain regions of the access JFETs; and   forming base intermediate regions for the sense amplifier BJTs in the semiconductor substrate that are self-aligned to the sense amplifier BJT emitter and base electrodes, the base intermediate regions being doped to the same conductivity type as base regions of the sense amplifier BJTs.