Semiconductor device and method of forming gate and metal line thereof

Abstract

A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

1 . A semiconductor device, comprising:
 a first MOS transistor pair formed adjacently on a substrate, wherein the first MOS transistor pair is formed symmetrically with respect to a predetermined reference line of a substrate; and   a second MOS transistor pair formed symmetrically with respect to the reference line on both sides of the first MOS transistor pair,   wherein the first and second MOS transistor pairs each include MOS transistors requiring the same electric characteristic.   
     
     
         2 . The semiconductor device as set forth in  claim 1 , wherein the first and second MOS transistor pairs include a differential pair which is controlled by a differential signal and operates to differential amplify, and a current mirror structure which is controlled by a common signal and generates the same current, respectively. 
     
     
         3 . The semiconductor device as set forth in  claim 1 , wherein gates of the first and second MOS transistor pairs are formed symmetrically with respect to the reference line, each of the gates being the same distance from the reference line. 
     
     
         4 . The semiconductor device as set forth in  claim 1 , wherein the first MOS transistor pair includes first MOS transistors having the same channel length as each other, and the second MOS transistor pair includes second MOS transistors having the same channel length as each other. 
     
     
         5 . The semiconductor device as set forth in  claim 4 , wherein a gate dummy pattern is further formed at both sides of each MOS transistor. 
     
     
         6 . The semiconductor device as set forth in  claim 5 , wherein a length of the gates of the second transistor pair is larger than a length of the gates of the first transistor pair, and a length of the gate dummy patterns formed between the first and second MOS transistor pairs is the same as the length of the gates of the second transistor pair. 
     
     
         7 . The semiconductor device as set forth in  claim 6 , wherein the gate dummy patterns between the first and second transistor pair includes a bar shaped main gate dummy and an auxiliary gate dummy connected to a portion of the bar shaped main gate dummy and protruding into a space left unoccupied by the first transistor pair having the gates with a shorter length. 
     
     
         8 . The semiconductor device as set forth in  claim 7 , wherein a length of the gate dummy patterns formed on the outsides of the second MOS transistor pair have a length the same as the length of the gates of the second MOS transistor pair. 
     
     
         9 . The semiconductor device as set forth in  claim 8 ,
 wherein the gate dummy patterns formed on the outsides of the second MOS transistor pair have a structure of two bar shaped gate dummies;   wherein each of the two bar shaped gate dummies have a length the same as the length of the gate of the second MOS transistor, and the two bar shaped gate dummies are integrated through a coupling part.