Semiconductor device and semiconductor device manufacturing method

Abstract

A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region.

1 . A semiconductor device manufacturing method comprising:
 selectively forming on a silicon substrate a blocking layer that blocks an epitaxial growth of a silicon germanium layer on the silicon substrate;   selectively epitaxially growing the silicon germanium layer on the silicon substrate using the blocking layer as a mask;   removing the blocking layer from the silicon substrate after the selectively epitaxially growing the silicon germanium layer on the silicon substrate;   forming a first semiconductor element on the silicon substrate by using the silicon germanium layer that is selectively epitaxially grown; and   forming a second semiconductor element on the silicon substrate without using the silicon germanium layer that is selectively epitaxially grown.   
     
     
         2 . The semiconductor device manufacturing method according to  claim 1 , wherein the blocking layer is a silicon oxide film, a silicon nitride film, or a phospho-silicate-glass (PSG) film. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the second semiconductor element is a P-channel field-effect transistor. 
     
     
         4 . The semiconductor device manufacturing method according to  claim 1 , further comprising:
 forming an element isolation region on the silicon substrate;   forming a gate electrode on the silicon substrate that is element-isolated by the element isolation region, via a gate insulating film;   forming a sidewall on a lateral side of the gate electrode; and   forming a recess on the silicon substrate between the element isolation region and the sidewall to sandwich a channel region beneath the gate electrode, wherein   the silicon germanium layer is selectively epitaxially grown on the silicon substrate to embed the recess with the silicon germanium layer.