Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy

Abstract

A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.

1 . A semiconductor integrated circuit device comprising:
 a first interconnection layer and a second interconnection layer disposed above the first interconnection layer;   a third interconnection layer disposed near the first and second interconnection layers;   a first conductor layer electrically connecting the first and second interconnection layers to each other;   a second conductor layer for redundancy, disposed by a side of the first conductor layer and between the first conductor layer and the third interconnection layer, and electrically connecting the first and second interconnection layers to each other; and   an extended portion of the second interconnection layer extended from a portion connected to the second conductor layer on the second interconnection layer toward the third interconnection layer, and having an extended dimension smaller than a minimum dimension prescribed in an interconnection line design rule.   
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein the first interconnection layer is an interconnection layer disposed on or above a semiconductor substrate, and the first and second conductor layers are via plugs. 
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , wherein the first interconnection layer is a diffusion region formed in a semiconductor substrate, and the first and second conductor layers are contact plugs. 
     
     
         4 . The semiconductor integrated circuit device according to  claim 1 , wherein the second interconnection layer has an interconnection line width in a direction perpendicular to a length direction of the second interconnection layer, and the first and second conductor layers have an interconnection line width in the direction perpendicular to the length direction of the second interconnection layer, and the interconnection line width of the first and second conductor layers is equal to the interconnection line width of the second interconnection layer. 
     
     
         5 . The semiconductor integrated circuit device according to  claim 1 , wherein a distance between the second interconnection layer and the third interconnection layer is equal to the minimum dimension prescribed in the interconnection line design rule.