Method for reducing dielectric overetch using a dielectric etch stop at a planar surface

Abstract

A method is described for reducing dielectric overetch. The method includes: ( 1 ) forming a substantially planar surface that coexposes conductive or semiconductor features and a dielectric etch stop layer, the conductive or semiconductor features including pillars that each include a vertically oriented diode; ( 2 ) depositing second dielectric fill directly on the planar surface; and ( 3 ) etching a void in the second dielectric fill, wherein the etch is selective between the second dielectric fill and the dielectric etch stop layer, wherein the etch stops on the dielectric etch stop layer. Numerous other aspects are provided.

1 . A method for reducing dielectric overetch, the method comprising:
 forming a substantially planar surface that coexposes conductive or semiconductor features and a dielectric etch stop layer, wherein the conductive or semiconductor features comprise pillars, each pillar comprising a vertically oriented diode;   depositing second dielectric fill directly on the planar surface; and   etching a void in the second dielectric fill,   wherein the etch is selective between the second dielectric fill and the dielectric etch stop layer, wherein the etch stops on the dielectric etch stop layer.   
     
     
         2 . The method of  claim 1 , wherein the dielectric etch stop layer comprises silicon nitride, silicon oxynitride, or silicon carbide. 
     
     
         3 . The method of  claim 1 , wherein forming the substantially planar surface comprises planarizing by chemical mechanical planarization (“CMP”). 
     
     
         4 . The method of  claim 1 , wherein forming the substantially planar surface comprises a selective overetch. 
     
     
         5 . The method of  claim 1 , wherein the second dielectric fill comprises silicon dioxide. 
     
     
         6 . The method of  claim 1 , wherein the conductive or semiconductor features comprise memory cells. 
     
     
         7 . The method of  claim 6 , wherein the memory cells comprise a monolithic three dimensional memory array. 
     
     
         8 . The method of  claim 1 , wherein the diodes comprise silicon and/or germanium. 
     
     
         9 . A method comprising:
 forming a plurality of first pillars, each first pillar comprising a vertically oriented semiconductor diode;   forming a substantially planar surface, the substantially planar surface coexposing the first pillars and a first dielectric material between the first pillars;   depositing a second dielectric material on the planar surface;   etching a plurality of trenches in the second dielectric material, wherein the etch is selective between the first dielectric material and the second dielectric material; and   forming first conductors in the trenches.   
     
     
         10 . The method of  claim 9 , wherein the semiconductor diodes comprise silicon and/or germanium. 
     
     
         11 . The method of  claim 9 , wherein the first dielectric material comprises silicon nitride, silicon oxynitride, or silicon carbide. 
     
     
         12 . The method of  claim 9 , wherein the second dielectric material comprises silicon dioxide. 
     
     
         13 . The method of  claim 9 , wherein forming the plurality of first pillars comprises:
 depositing a semiconductor layer stack above underlying conductors; and   patterning and etching the semiconductor layer stack to form the first pillars.   
     
     
         14 . The method of  claim 9 , further comprising forming second pillars above the first conductors. 
     
     
         15 . The method of  claim 9 , wherein the first pillars and first conductors comprise a first memory level. 
     
     
         16 . The method of  claim 15 , further comprising forming at least a second memory level above the first memory level. 
     
     
         17 . The method of  claim 16 , wherein the first and second memory levels comprise vertically stacked memory levels in a monolithic three dimensional memory array. 
     
     
         18 . A method for minimizing dielectric overetch in a monolithic three dimensional memory array, the method comprising:
 forming a first memory level by:
 forming first bottom conductors; 
 forming first pillars above the first bottom conductors, the first pillars separated by a first dielectric material, wherein each of the first pillars comprises a vertically oriented semiconductor diode; 
 depositing a second dielectric material on the first pillars; 
 etching trenches in the second dielectric material, wherein the etch is selective between the first dielectric material and the second dielectric material; and 
 forming first top conductors in the trenches; and 
   monolithically forming at least a second memory level above the first memory level.   
     
     
         19 . The method of  claim 18 , wherein the first memory level comprises a plurality of first memory cells, each of the first memory cells comprising:
 a portion of one of the first bottom conductors;   a first pillar; and   a portion of one of the first top conductors.   
     
     
         20 . The method of  claim 18 , wherein the step of forming at least a second memory level above the first memory level comprises forming second pillars above the first top conductors.