Display substrate

Abstract

A display substrate includes a plurality of gate lines extending in a first direction and arranged in a second direction in a display area of the display substrate, an alignment film formed in the display area and in an end area adjacent to end portions of the gate lines in a peripheral area surrounding the display area, and a plurality of circuit stages formed in the end area to connect to the gate lines and a dummy stage connected to a last circuit stage of the circuit stages. Each of the circuit stages includes a gate driving circuit disposed at the higher portion the gate line corresponding to the circuit stages and a gate connecting line formed in the peripheral area between the display area and the gate driving circuit to connect each of the circuit stages with each of the gate lines.

1 . A display substrate comprising:
 a plurality of spaced apart gate lines each extending in a first direction and formed in a display area of the display substrate;   an alignment film formed in the display area and also in an end area adjacent to end portions of the gate lines in a peripheral area surrounding the display area;   a gate driving circuit formed in the end area and including a plurality of circuit stages connected to the gate lines and a dummy stage connected to a last circuit stage of the circuit stages, each of the circuit stages being disposed at the higher portion of the gate line corresponding to the circuit stage; and   a gate connecting line formed in the peripheral area between the display area and the gate driving circuit to connect each of the circuit stages with each of the gate lines.   
     
     
         2 . The display substrate of  claim 1 , further comprising a sub-gate line formed adjacent to each of the gate lines in the display area,
 wherein the circuit stages comprise:   first sub-stages formed in the end area and connected to first to m-th gate lines (m is a natural number) of the gate lines; and   second sub-stages formed in the end area, connected to (m+1)-th to n-th gate lines (n is a natural number more than m) and connected to first to (n−m)-th sub-gate lines,   wherein the gate driving circuit further comprises third sub-stages connected to ((n−m)+1)-th to n-th sub-gate lines.   
     
     
         3 . The display substrate of  claim 2 , wherein the dummy stage is connected to a last third sub-stage of the third sub-stages. 
     
     
         4 . The display substrate of  claim 2 , wherein a pixel formed in the display area comprises:
 first and second transistors connected to each of the gate lines; and   a third transistor connected to a sub-gate line adjacent to the gate line, and the first and second transistors.   
     
     
         5 . The display substrate of  claim 1 , further comprising a wiring part adjacent to the gate driving circuit and formed in the end area, wherein the wiring part comprises;
 a Vss voltage supplying line extending in the second direction, and supplying a Vss voltage supply signal;   a clock line extending in the second direction, and applying a clock signal;   a voltage supplying cross-connecting line extending in the first direction to connect the Vss voltage supply line to the gate driving circuit; and   a clock cross-connecting line extending in the first direction to connect the clock line to the gate driving circuit.   
     
     
         6 . The display substrate of  claim 5 , wherein a portion in which the voltage supplying line and the clock connecting line intersect with each other and a portion in which the clock line and the voltage supplying connecting line intersect with each other are disposed in the end area. 
     
     
         7 . A display substrate comprising;
 a plurality of gate lines extending in a first direction, and arranged in a second direction in a display area of the display substrate;   an alignment film formed in the display area and in a first area adjacent to end portions of the gate lines in a peripheral area surrounding the display area;   a gate driving circuit comprising a plurality of circuit stages and a dummy stage, the circuit stages being formed in the first area and being connected to the gate lines, the dummy stage being connected to a last circuit stage of the circuit stages and being formed in a second area arranged in the second direction of the first area; and   a wiring part formed in the peripheral area and comprising a first signal line, a second signal line and a first cross-connecting line, the first signal line extending in the second direction and being adjacent to the gate driving circuit, the second signal line being disposed between the first signal line and the gate driving circuit, the first cross-connecting line connecting the second signal line to the dummy stage, a portion of the first cross-connecting line insulatively crossing with the second signal line being formed in the first area.   
     
     
         8 . The display substrate of  claim 7 , wherein the first connecting line extends from the first signal line disposed in the first area to the second signal line of the first area to intersect with the second signal line, and extends to the second area. 
     
     
         9 . The display substrate of  claim 8 , wherein the first signal line comprises a voltage supplying line applying a voltage supplying signal, and
 the second signal line comprises a clock line applying a clock signal.   
     
     
         10 . The display substrate of  claim 7 , wherein the first connecting line extends from the first signal line disposed in the second area to the second signal line of the first area to intersect with the second signal line, and extends to the second area. 
     
     
         11 . The display substrate of  claim 10 , wherein the first signal line comprises a clock line applying a clock signal, and
 the second signal line comprises a voltage supplying line applying a voltage supplying signal.   
     
     
         12 . The display substrate of  claim 7 , wherein each of the first and second signal lines extends from the first area to the second area. 
     
     
         13 . The display substrate of  claim 7 , further comprising a plurality of sub-gate lines extending in the first direction in the display area,
 wherein the circuit stages comprise:   first sub-stages formed in the first area and connected to first to m-th gate lines (m is a natural number) of the gate lines; and   second sub-stages formed in the first area, connected to (m+1)-th to n-th gate lines (n is a natural number more than m) and connected to first to (n−m)-th sub-gate lines,   wherein the gate driving circuit further comprises third sub-stages connected to ((n−m)+1)-th to n-th sub-gate lines.   
     
     
         14 . The display substrate of  claim 13 , wherein the wiring part further comprises a second connecting line connecting the first signal line to the third sub-stage, and a portion of the second connecting line intersecting with the second signal line is disposed in the first area. 
     
     
         15 . The display substrate of  claim 13 , wherein the second and third sub-stages are disposed at a lower portion of the sub-gate lines corresponding to the second and third sub-stages. 
     
     
         16 . The display substrate of  claim 15 , further comprising a gate connecting lines formed between the gate driving circuit and the sub-gate lines and connecting the second and third sub-stages to the sub-gate lines. 
     
     
         17 . The display substrate of  claim 13 , wherein a pixel formed in the display area comprises:
 first and second transistors connected to each of the gate lines; and   a third transistor connected to a sub-gate line adjacent to the gate line, and the first and second transistors.