US2011302363A1PendingUtilityA1

Non-volatile memories, cards, and systems including shallow trench isolation structures with buried bit lines

Assignee: KWON WOOK HYUNPriority: Apr 27, 2007Filed: Aug 22, 2011Published: Dec 8, 2011
Est. expiryApr 27, 2027(~0.7 yrs left)· nominal 20-yr term from priority
Inventors:Wook-Hyun Kwon
H10W 10/17H10W 10/014H10D 30/681H10D 30/6894G11C 16/0416H10B 41/30H10B 69/00
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Claims

Abstract

A non-volatile memory device can include a buried bit line in a substrate of a non-volatile memory device and a self-aligned shallow trench isolation region in the substrate that is self-aligned to the buried bit line.

Claims

exact text as granted — not AI-modified
1 . A non-volatile memory device comprising:
 a buried bit line in a substrate of a non-volatile memory device; and   a self-aligned shallow trench isolation region in the substrate self-aligned to the buried bit line.   
     
     
         2 . The non-volatile memory device according to  claim 1  further comprising:
 a gate structure having the buried bit line self-aligned thereto, wherein the gate structure includes a protruding portion that extends into the substrate beyond a lower surface of the buried bit line. 
 
     
     
         3 . An electronic system comprising:
 a processor configured to coordinate operations of an electronic system;   a volatile memory, electrically coupled to the processor, configured to store and retrieve data responsive processor operations;   a system interface, electrically coupled to the processor, configured to provide communications between the processor and external systems; and   a non-volatile memory, electrically coupled to the processor, including at least one non-volatile memory device comprising:
 a buried bit line in a substrate of a non-volatile memory device; and 
 a self-aligned shallow trench isolation region in the substrate self-aligned to the buried bit line. 
   
     
     
         4 . The electronic system according to  claim 3  further comprising:
 a gate structure having the buried bit line self-aligned thereto, wherein the gate structure includes a protruding portion that extends into the substrate beyond a lower surface of the buried bit line. 
 
     
     
         5 . A memory card comprising:
 a non-volatile memory controller configured to coordinate operations of the memory card; and   a non-volatile memory, electrically coupled to the non-volatile memory controller, including a non-volatile memory comprising:
 a buried bit line in a substrate of a non-volatile memory; and 
 a self-aligned shallow trench isolation region in the substrate self-aligned to the buried bit line. 
   
     
     
         6 . The memory card according to  claim 5  further comprising:
 a gate structure having the buried bit line self-aligned thereto, wherein the gate structure includes a protruding portion that extends into the substrate beyond a lower surface of the buried bit line. 
 
     
     
         7 . The memory card according to  claim 6  wherein the gate structure comprises a U-shaped floating gate electrode.

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