US2011297550A1PendingUtilityA1

Method of forming the structure of thermal resistive layer

Assignee: CHANG JUNG-FANGPriority: Nov 4, 2004Filed: Aug 19, 2011Published: Dec 8, 2011
Est. expiryNov 4, 2024(expired)· nominal 20-yr term from priority
H10D 86/0229H10D 30/0321H10D 30/0316H10D 30/0314H10D 30/6758B32B 5/18B32B 2255/10Y10T428/249969Y10T428/249971B32B 27/08Y10T428/249987B32B 15/16B32B 15/00Y10T428/31678B32B 2250/40Y10T428/249974B32B 3/20Y10T428/249953B32B 3/266B32B 5/16Y10T428/24997B32B 15/08B32B 2255/205B32B 2307/704B32B 27/14B32B 27/06B32B 3/085B32B 2264/102Y10T428/24999Y10T428/249975B32B 2457/20B32B 2307/306H10K 50/87H10K 77/10
44
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

The prevent disclosure discloses a structure of thermal resistive layer and the method of forming the same. The thermal resistive structures, formed on a plastic substrate, comprises a porous layer, formed on said plastic substrate, including a plurality of oxides of hollow structure, and a buffer layer, formed on said porous layer, wherein said porous layer can protect said plastic substrate from damage caused by the heat generated during manufacturing process. With the structure and method disclosed above, making a thin film transistor and forming electronic devices on the plastic substrate in the technology of Low Temperature PolySilicon, i.e. LTPS, without changing any parameters is possible.

Claims

exact text as granted — not AI-modified
1 . A method for forming a structure of thermal resistive layer on a plastic substrate comprising the steps of:
 forming a material layer on said plastic substrate;   transforming said material layer into a porous template layer with a specific thickness by anodizing; and   forming a buffer layer on said porous template layer.   
     
     
         2 . The method according to  claim 1 , wherein said buffer layer is substantially a silicon oxide. 
     
     
         3 . The method according to  claim 1 , further comprising forming a planarization layer between said buffer layer and said porous template layer. 
     
     
         4 . The method according to  claim 3 , wherein said planarization layer is a material selected from the group consisting of polymer, and inorganic material. 
     
     
         5 . The method according to  claim 1 , wherein said material layer is a material selected from the group consisting of silicon, titanium, zinc, and aluminum. 
     
     
         6 . The method according to  claim 1 , wherein said porous template layer further comprises a plurality of oxides of hollow structure which are material selected from the group consisting of silicon oxide, titanium oxide, zinc oxide, and aluminum oxide. 
     
     
         7 . The method according to  claim 6 , wherein the shape of said oxide of hollow structure is selected from the group consisting of sphere, column, and disk. 
     
     
         8 . The method according to  claim 1 , further comprising a conductive layer formed between said plastic substrate and said material layer. 
     
     
         9 . The method according to  claim 8 , wherein said conductive layer is substantially an indium tin oxide.

Join the waitlist — get patent alerts

Track US2011297550A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.