Wafer level integration module with interconnects

Abstract

A wafer level integration module and method for forming are disclosed. A construction includes semiconductor functional device fabrication carried out after interconnect structures are processed on a bare wafer. Interconnect structures are formed in a first side of the wafer. An insulation layer is deposited on the first side of the wafer to insulate walls of the interconnect structures. A conductive layer is deposited on the insulation layer filling the interconnect structures so as to contact the insulation layer on the walls of the interconnect structures. The conductive layer forms interconnection contacts on the first side of the wafer and interconnection vias extending into the wafer. The first conductive layer including the interconnection contacts is exposed on the first side of the wafer and a semiconductor functional device is formed on the first side of the wafer. The semiconductor functional device is interconnected with the interconnection contacts during the fabricating. At least portions of the conductive layer associated with the interconnection vias are exposed from the second side of the wafer.

1 . A method of fabricating a wafer level integration module according to a construction whereby semiconductor functional device fabrication is carried out only after interconnect structures are processed on a bare wafer comprising:
 forming the interconnect structures in a first side of the wafer;   depositing a first insulation layer on the first side of the wafer so as to insulate walls of the interconnect structures;   depositing a first conductive layer on the insulation layer, the first conductive layer filling the interconnect structures so as to contact the first insulation layer on the walls of the interconnect structures, the first conductive layer forming interconnection contacts on the first side of the wafer and interconnection vias extending into the wafer;   exposing the first conductive layer to form interconnection contacts on the first side of the wafer;   fabricating a semiconductor functional device on the first side of the wafer, the semiconductor functional device interconnected with the interconnection contacts during the fabricating the semiconductor functional device; and   exposing from the second side of the wafer, at least portions of the first conductive layer associated with the interconnection vias.   
     
     
         2 . The method of  claim 1 , wherein the structures include microstructures. 
     
     
         3 . The method of  claim 1 , wherein the conductive layer is a high temperature conductive film. 
     
     
         4 . The method of  claim 1 , wherein the exposing the first conductive layer, including the high temperature conductive film includes exposing by chemical mechanical polishing. 
     
     
         5 . The method of  claim 1 , wherein the exposing the first conductive layer, including the high temperature conductive film includes exposing by back grinding. 
     
     
         6 . The method of  claim 1 , further comprising providing a protection substrate to cover the first side of the wafer so as to protect the semiconductor functional device. 
     
     
         7 . The method of  claim 1 , further comprising depositing a second insulation layer on the second side of the wafer; patterning the second insulation layer and exposing the interconnection vias; depositing a second conductive layer on the patterned second insulation layer for contact with external devices. 
     
     
         8 . The method of  claim 1 , wherein the fabricating the semiconductor functional devices comprises depositing additional layers for forming a new functional device. 
     
     
         9 . The method of  claim 8  wherein the additional layers form a plurality of the new functional devices. 
     
     
         10 . The method of  claim 8  wherein the additional layers are formed in a stack formation. 
     
     
         11 . The method of  claim 1 , wherein the interconnect via structures, the semiconductor functional device, the first conductive layer filling the interconnect structures, interconnection contacts and interconnection vias are formed as one of a plurality of dies formed on the wafer. 
     
     
         12 . The method of  claim 11  further comprising separating the plurality of dies along separation zones. 
     
     
         13 . The method of  claim 8 , wherein the semiconductor functional device includes a transistor. 
     
     
         14 . The method of  claims 9  wherein the plurality of semiconductor functional devices include transistors. 
     
     
         15 . The method of  claim 1 , further comprising testing the semiconductor functional device after fabrication. 
     
     
         16 . The method of  claim 15  wherein testing the semiconductor functional device comprises forming test pads on the first side of the wafer. 
     
     
         17 . The method of  claim 15  further comprising removing the test pads after testing and before fabrication of a subsequent semiconductor functional device. 
     
     
         18 . The method of  claim 1 , further comprising depositing a third insulation layer to the first conductive layer when the first conductive layer is applied to the interconnect structures in a manner so as to partially fill the interconnect structures to control a resistance of the resulting interconnection vias to planarize and protect the first conductive layer on the first side of the wafer. 
     
     
         19 . A wafer level integration module comprising:
 interconnect structures formed on a first side of the wafer, the interconnect structures having walls including a first insulation layer applied thereon from the first side of the wafer;   a first conductive layer applied on the insulation layer on the walls of the interconnect structures, the first conductive layer filling the interconnect structures and forming interconnection contacts on the first side of the wafer and interconnection vias extending into the wafer to a given depth;   interconnection contacts on the first side of the wafer, the interconnection contacts including exposed portions of the first conductive layer;   a semiconductor functional device fabricated on the first side of the wafer, the semiconductor functional device interconnected with the interconnection contacts during the fabricating the semiconductor functional device after the interconnect structures are formed; and   interconnect via contacts on the second side of the wafer, the interconnect via contacts formed from exposed portions of the first conductive layer associated with the interconnection vias.   
     
     
         20 . The wafer level integration module of  claim 19 , wherein the exposed portions on the second side of the wafer include chemical mechanical polished exposed portions. 
     
     
         21 . The wafer level integration module of  claim 19 , wherein the exposed portions on the second side of the wafer include back grinded exposed portions. 
     
     
         22 . The wafer level integration module of  claim 19 , further comprising a protection substrate on the first side of the wafer that covers the semiconductor functional device. 
     
     
         23 . The wafer level integration module of  claim 19 , further comprising:
 a second insulation layer on the second side of the wafer; the second insulation layer having an interconnection pattern that exposes at least some of the interconnection vias; and   depositing a second conductive layer on the patterned second insulation layer for contact with external devices.   
     
     
         24 . The wafer level integration module of  claim 19 , further comprising additional layers constituting a new functional device. 
     
     
         25 . The wafer level integration module of  claim 19 , further comprising test pads on the first side of the wafer, the test pads connected to the functional semiconductor device. 
     
     
         26 . wafer level integration module of  claim 19 , further comprising a resistivity controlling layer applied to the first conductive layer on the first side of the wafer, the resistivity controlling layer controlling a resistivity of the interconnection structures.