US2011275204A1PendingUtilityA1

Method of fabricating a semiconductor device including ion implantation at a tilt angle in exposed regions

Assignee: HYNIX SEMICONDUCTOR INCPriority: Dec 28, 2006Filed: Jul 19, 2011Published: Nov 10, 2011
Est. expiryDec 28, 2026(~0.4 yrs left)· nominal 20-yr term from priority
H10P 30/222H10D 62/371H10D 62/307H10B 12/05H10P 30/221
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Claims

Abstract

A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. An impurity layer for suppressing punch-through will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.

Claims

exact text as granted — not AI-modified
1 .- 8 . (canceled) 
     
     
         9 . A method of fabricating a semiconductor device, the method comprising:
 forming a mask pattern for defining a region on a semiconductor substrate, wherein an impurity layer for suppressing punch-through will be formed in the defined region; and   implanting dopant ions into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.   
     
     
         10 . The method according to  claim 9 , wherein the mask pattern is formed to expose the region in which the impurity layer for suppressing the punch-through of an NMOS transistor will be formed, and wherein implanting the dopant ions further comprises implanting B 11  ions at a concentration of 0.5×10 13  atoms/cm 2  to 1×10 13  atoms/cm 2  and at an energy of approximately 30 to 80 KeV. 
     
     
         11 . The method according to  claim 9 , wherein the mask pattern is formed to expose the region in which the impurity layer for suppressing the punch-through of a PMOS transistor will be formed, and wherein implanting the dopant ions further comprises implanting As 75  ions at a concentration of 9.4×10 12  atoms/cm 2  and at an energy of 150 KeV. 
     
     
         12 .- 14 . (canceled)

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