Nonvolatile memory device

Abstract

A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously.

1 . A nonvolatile memory device comprising a nonvolatile memory and a controller unit for the nonvolatile memory, wherein:
 the nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively;   the nonvolatile memory includes a regulator configured to supply a power supply voltage to both of the first and second logic sections of the nonvolatile memory and the controller unit; and   the power supply voltage from the regulator is supplied to the first logic section of the nonvolatile memory provided with the regulator, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously.   
     
     
         2 . A nonvolatile memory device comprising a nonvolatile memory and a controller unit for the nonvolatile memory, wherein:
 the nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively;   the nonvolatile memory includes an oscillator configured to supply a clock to both of the first and second logic sections of the nonvolatile memory and the controller unit; and   the clock from the oscillator is supplied to the first logic section of the nonvolatile memory provided with the oscillator, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously.   
     
     
         3 . The nonvolatile memory device according to  claim 1 , wherein:
 the nonvolatile memory includes a reference voltage circuit configured to generate a reference voltage; and   the reference voltage from the reference voltage circuit is supplied to a first regulator in the nonvolatile memory provided with the reference voltage circuit, and also to a second regulator provided in the controller unit and/or a regulator of at least one added nonvolatile memory via a buffer amplifier.   
     
     
         4 . The nonvolatile memory device according to  claim 2 , wherein:
 the nonvolatile memory includes a reference oscillator configured to generate a reference clock; and   the reference clock from the reference oscillator is supplied to a first frequency multiplier in the nonvolatile memory provided with the reference oscillator, and also to a second frequency multiplier provided in the controller unit and/or a frequency multiplier of at least one added nonvolatile memory via a buffer amplifier.   
     
     
         5 . The nonvolatile memory device according to  claim 3 , wherein regulator voltages output from the first and second regulators and the regulator of the at least one added are set to mutually different voltages. 
     
     
         6 . The nonvolatile memory device according to  claim 4 , wherein frequencies of clock signals output from the first and second frequency multipliers and the frequency multiplier of the at least one added nonvolatile memory are set to mutually different frequencies. 
     
     
         7 . The nonvolatile memory device according to  claim 1 , wherein the first and second logic sections can operate using a predetermined stabilized voltage from the regulator as a power supply voltage, while unless the voltage detector detects that a predetermined minimum guaranteed voltage, which is higher than the stabilized voltage, is secured, the first and second logic sections are not reset, and the first and second logic sections do not start operating. 
     
     
         8 . The nonvolatile memory device according to  claim 7 , wherein for start of operation of the first and second logic sections, even if whether an input signal from a host bus is at a high level or a low level is normally detected in the first and second logic sections, the input signal is not employed as a digital signal of a high level/low level from the host bus in the first and second logic sections unless the voltage detector detects a voltage equal to or exceeding the predetermined minimum guaranteed voltage.