Pixel having an organic light emitting diode and method of fabricating the pixel

Abstract

A pixel having an organic light emitting diode (OLED) and method for fabricating the pixel is provided. A planarization dielectric layer is provided between a thin-film transistor (TFT) based backplane and OLED layers. A through via between the TFT backplane and the OLED layers forms a sidewall angle of less than 90 degrees to the TFT backplane. The via area and edges of an OLED bottom electrode pattern may be covered with a dielectric cap.

1 . A pixel having a vertical architecture, comprising: an organic light emitting diode (OLED) device having a bottom electrode, one or more OLED layers and a top electrode for emitting light;
 a thin-film transistor (TFT) based backplane for electrically driving, the OLED device, the TFT based backplane being vertically integrated with the OLED layers;   and a planarization dielectric layer provided between the TFT based backplane and the OLED bottom electrode so as to planarize the vertical profile on the TFT based backplane.   
     
     
         2 . The pixel as claimed in  claim 1  further comprising a via for providing a communication path between the TFT backplane and the OLED device through the planarization dielectric layer, wherein the sidewall of the via in the planarization layer is sloped against the TFT based backplane. 
     
     
         3 . The pixel as claimed in  claim 1 , further comprising an additional dielectric layer provided between the OLED bottom electrode and the OLED layers, which is patterned in such a way that it insulates the OLED layers from the OLED bottom electrode at pixel edges and in and around the via while leaving the rest of the OLED bottom electrode in the direct contact with the OLED layers. 
     
     
         4 . The pixel as claimed in  claim 1 , wherein the pixel has a roughness of the order of 1 nm on the planarization dielectric layer and subsequent electrode layer. 
     
     
         5 . The pixel as claimed in  claim 1 , further comprising continuous sidewall coverage by pixel electrode material in the via profile in the planarization dielectric layer. 
     
     
         6 . The pixel as claimed in  claim 1 , further comprising a shield electrode formed over the TFT. 
     
     
         7 . The pixel as claimed in  claim 2 , wherein the TFT based backplane includes:
 a substrate;   gate, source and drain nodes;   an interlayer dielectric layer on the source and drain nodes; and   an interconnection plate patterned on a via of the interlayer dielectric layer and being connected to the source or drain node;   wherein the planarization dielectric layer planarizes the vertical profile on the substrate with the fabricated TFT based backplane, and the sloped via providing the communication path through the interconnection plate.   
     
     
         8 . The pixel as claimed in  claim 7 , further comprising a contact plate on the interlayer dielectric layer, which is formed such that the interconnection plate overlaps a part of the contact plate, the sloped via providing the communication path through the contact plate. 
     
     
         9 . The pixel as claimed in  claim 7 , further comprising a shield electrode disposed between the planalization dielectric layer and the interlayer dielectric layer, which is located separately from the interconnection plate. 
     
     
         10 . The pixel as claimed in  claim 2 , wherein the TFT based backplane includes: a substrate;
 gate, source and drain nodes;   an interlayer dielectric layer on the source and drain nodes;   a contact plate which is formed such that the source or drain material overlaps the contact plate;   wherein the planarization dielectric layer planarizes the vertical profile on the substrate with the fabricated TFT based backplane, and the sloped via providing the communication path through the contact plate.   
     
     
         11 . The pixel as claimed in  claim 10 , further comprising a shield electrode is formed separately from the interconnection plate the contact plate. 
     
     
         12 . The pixel as claimed in  claim 1 , wherein the planalization dielectric layer includes photosensitive benzocylobutene (BCB), the slope of the via being adjusted by the exposure time of the photosensitive BCB. 
     
     
         13 . The pixel as claimed in  claim 3 , wherein the additional dielectric layer includes polymer dielectric or inorganic insulator. 
     
     
         14 . The pixel as claimed in  claim 3 , wherein the additional dielectric layer includes material selected from the group from BCB, polyimide, polymer dielectric, silicon nitride and a thin film inorganic. 
     
     
         15 . A method of fabricating a pixel, the pixel having an organic light emitting diode (OLED) bottom electrode, one or more OLED layers on the OLED bottom electrode, and a thin-film transistor (TFT) based backplane for electrically driving the OLED and including a substrate, the method comprising the steps of: providing the TFT based backplane; and
 providing a dielectric layer on the TFT based backplane, including the step of planarizing a vertical profile in the dielectric layer so as to planarize the vertical profile on the substrate with the TFT based backplane.   
     
     
         16 . A method as claimed in  claim 15 , further comprising the step of forming a via which provides a communication path between the TFT backplane and the OLED device through the planarization dielectric layer, such that the sidewall of the via in the planarization layer is sloped against the TFT based backplane. 
     
     
         17 . A method as claimed in  claim 15 , further comprising the step of providing an additional dielectric layer between the OLED bottom electrode and the OLED layers, which is patterned in such a way that it insulates the OLED layers from the OLED bottom electrode at pixel edges and in and around the via while leaving the rest of the OLED bottom electrode in the direct contact with the OLED layers. 
     
     
         18 . A method as claimed in  claim 15 , wherein the planarization dielectric layer including photosensitive benzocylobutene (BCB), further comprising the step of adjusting the exposure time of the photosensitive BCB such that the sidewall of the via in the planarization layer is sloped against the TFT based backplane. 
     
     
         19 . A method as claimed in  claim 15 , wherein the pixel is formed such that the pixel has a roughness of the order of 1 nm on the planarization dielectric layer and subsequent electrode layer. 
     
     
         20 . A method as claimed in  claim 15 , further comprising the step of providing continuous sidewall coverage by pixel electrode material in the via profile in the planarization dielectric layer.