Representing binary code as a circuit

Abstract

A high level intermediate representation of a binary is generated. Circuit nodes from the high level intermediate representation are built, wherein a circuit node represents an operation in the high level intermediate representation. The circuit nodes are connecting using a flow analysis of the binary to build a circuit that represents the binary.

1 . A method comprising generating, by a computer, interconnected circuit nodes that represent binary code, wherein one of the generated circuit nodes is configured to be enabled and disabled based on a conditional instruction of the binary code. 
     
     
         2 . The method of  claim 1  further comprising performing a flow analysis of the binary code. 
     
     
         3 . The method of  claim 2  further comprising generating a high-level intermediate representation based at least in part on the flow analysis. 
     
     
         4 . The method of  claim 3  wherein the generating the interconnected circuit nodes is based on the high-level intermediate representation. 
     
     
         5 . The method of  claim 1  further comprising generating an intermediate representation of the binary code. 
     
     
         6 . The method of  claim 5  further comprising generating a high-level intermediate representation based at least in part on the intermediate representation. 
     
     
         7 . The method of  claim 6  wherein the generating the interconnected circuit nodes is based on the high-level intermediate representation. 
     
     
         8 . At least one computer storage media comprising computer-executable instructions that, when executed by a computer, cause the computer to perform a method comprising generating, by a computer, interconnected circuit nodes that represent binary code, wherein one of the generated circuit nodes is configured to be enabled and disabled based on a conditional instruction of the binary code. 
     
     
         9 . The at least one computer storage media of  claim 8 , the method further comprising performing a flow analysis of the binary code. 
     
     
         10 . The at least one computer storage media of  claim 9 , the method further comprising generating a high-level intermediate representation based at least in part on the flow analysis. 
     
     
         11 . The at least one computer storage media of  claim 10  wherein the generating the interconnected circuit nodes is based on the high-level intermediate representation. 
     
     
         12 . The at least one computer storage media of  claim 8 , the method further comprising generating an intermediate representation of the binary code. 
     
     
         13 . The at least one computer storage media of  claim 12 , the method further comprising generating a high-level intermediate representation based at least in part on the intermediate representation. 
     
     
         14 . The at least one computer storage media of  claim 13  wherein the generating the interconnected circuit nodes is based on the high-level intermediate representation. 
     
     
         15 . A system comprising a computer configured for generating interconnected circuit nodes that represent binary code, wherein one of the generated circuit nodes is configured to be enabled and disabled based on a conditional instruction of the binary code. 
     
     
         16 . The system of  claim 15 , the computer further configured for performing a flow analysis of the binary code. 
     
     
         17 . The system of  claim 16 , the computer further configured for generating a high-level intermediate representation based at least in part on the flow analysis. 
     
     
         18 . The system of  claim 17  wherein the generating the interconnected circuit nodes is based on the high-level intermediate representation. 
     
     
         19 . The system of  claim 15 , the computer further configured for generating an intermediate representation of the binary code. 
     
     
         20 . The system of  claim 19 , the computer further configured for generating a high-level intermediate representation based at least in part on the intermediate representation.