Node-based transient acceleration method for simulating circuits with latency

Abstract

When modeling a circuit, transient analysis is an important part of the analysis. However, for transient analyses, device model evaluating can consume a considerable amount of time, when using conventional simulators. Here, a simulator is provided that allows for detection of latency on a node-by-node basis, as opposed to a device-by-device basis with conventional simulators. Using this type of analysis can greatly reduce the time of an analysis, which affects both the cost of a product and its time to market.

1 . A method comprising:
 receiving a product specification for a circuit having a plurality of active devices that are coupled to one another through a plurality of nodes;   generating a matrix representation of a system of equations that is generally representative of the circuit, wherein the matrix representation has a plurality of matrix rows, and wherein each matrix row corresponds to at least one of the nodes;   iteratively solving the matrix representation of the system of equations for each of a plurality of transient time points to generate a simulation of the circuit, wherein the step of iteratively solving includes the substeps of:
 determining if each node satisfies a latency condition for each iteration of each transient time point; and 
 using a previous iteration for each matrix row when each of its nodes satisfies the latency condition. 
   
     
     
         2 . The method of  claim 1 , wherein the latency condition further comprises a plurality of latency conditions. 
     
     
         3 . The method of  claim 2 , wherein the latency conditions are based at least in part on Newton convergence criteria. 
     
     
         4 . The method of  claim 3 , wherein the substep of determining if each node satisfies the latency conditions for each iteration of each transient time point further comprises:
 determining, for each node, the absolute value of the sum of currents for each iteration of each transient time point;   determining, for each node, the absolute value of the change in voltage for each iteration of each transient time point;   comparing, for each iteration of each transient time point, each of the absolute value of the sum of currents and the absolute value of the change in voltage to a node latency tolerance; and   determining that at least one of the nodes satisfies the latency conditions for at least one iteration for at least one of the transient time points if its absolute value of the sum of currents and its absolute value of the change in voltage are each less than the node latency tolerance.   
     
     
         5 . A processor having a computer program product embodied thereon, the computer program product comprising:
 computer code for receiving a product specification for a circuit having a plurality of active devices that are coupled to one another through a plurality of nodes;   computer code for generating a matrix representation of a system of equations that is generally representative of the circuit, wherein the matrix representation has a plurality of matrix rows, and wherein each matrix row corresponds to at least one of the nodes;   computer code for iteratively solving the matrix representation of the system of equations for each of a plurality of transient time points to generate a simulation of the circuit, wherein the step of iteratively solving includes the substeps of:
 computer code for determining if each node satisfies a latency condition for each iteration of each transient time point; and 
 computer code for using a previous iteration for each matrix row when each of its nodes satisfies the latency condition. 
   
     
     
         6 . The computer program product of  claim 5 , wherein the latency condition further comprises a plurality of latency conditions. 
     
     
         7 . The computer program product of  claim 6 , wherein the latency conditions are based at least in part on Newton convergence criteria. 
     
     
         8 . The computer program product of  claim 7 , wherein the computer code for determining if each node satisfies the latency conditions for iteration of each transient time point further comprises:
 computer code for determining, for each node, the absolute value of the sum of currents for each iteration of each transient time point;   computer code for determining, for each node, the absolute value of the change in voltage for each iteration of each transient time point;   computer code for comparing, for each iteration of each transient time point, each of the absolute value of the sum of currents and the absolute value of the change in voltage to a node latency tolerance; and   computer code for determining that at least one of the nodes satisfies the latency conditions for at least one of the transient time points if its absolute value of the sum of currents and its absolute value of the change in voltage are each less than the node latency tolerance.   
     
     
         9 . An apparatus comprising:
 a storage medium having a matrix solver, a device evaluator, a latency detector, a convergence checker, and a matrix loader stored thereon, and   a processor having an engine embodied thereon that is in communication with the storage medium, wherein the engine:
 receives a product specification for a circuit having a plurality of active devices that are coupled to one another through a plurality of nodes; 
 generates, with the matrix loader and the device evaluator, a matrix representation of a system of equations that is generally representative of the circuit, wherein the matrix representation has a plurality of matrix rows, and wherein each matrix row corresponds to at least one of the nodes; 
 iteratively solves, with the matrix solver, the matrix loader, the latency detector, ad the convergence checker, the matrix representation of the system of equations for each of a plurality of transient time points to generate a simulation of the circuit, wherein the engine iteratively solves by:
 determining with the latency detector if each node satisfies a latency condition for each iteration of each transient time point; and 
 using a previous iteration with the matrix loader for each matrix row when each of its nodes satisfies the latency condition. 
 
   
     
     
         10 . The apparatus of  claim 9 , wherein the latency condition further comprises a plurality of latency conditions. 
     
     
         11 . The apparatus of  claim 10 , wherein the latency conditions are based at least in part on Newton convergence criteria. 
     
     
         12 . The apparatus of  claim 11 , wherein the engine, with the latency detector:
 determines, for each node, the absolute value of the sum of currents for each iteration of each transient time point;   determines, for each node, the absolute value of the change in voltage for each iteration of each transient time point;   compares, for each transient time point, each of the absolute value of the sum of currents and the absolute value of the change in voltage to a node latency tolerance; and   determines that at least one of the nodes satisfies the latency conditions for at least one of the transient time points if its absolute value of the sum of currents and its absolute value of the change in voltage are each less than the node latency tolerance.   
     
     
         13 . The apparatus of  claim 9 , wherein the processor further comprises a personal computer. 
     
     
         14 . The apparatus of  claim 9 , wherein the processor further comprises a plurality of processor distributed across a computer network.