Semiconductor memory device

Abstract

A semiconductor memory device comprises a comparing unit that comprises a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell; first and second bit lines connected to inputs of the comparing unit; a first memory cell connected to the first bit line; a second memory cell connected to the second bit line; a first reference cell acting as the reference cell; a second reference cell acting as another reference cell; a potential line that supplies the reference potential to the first and second reference cells; and a dummy cell comprising a coupling capacitor that stabilizes potential of the potential line.

1 . A semiconductor memory device that reads data by comparing a potential of a memory cell with a reference potential of a reference cell, comprising:
 first and second bit lines connected to a same sense amplifier;   a first memory cell connected to said first bit line;   a second memory cell connected to said second bit line;   a first reference cell connected to said first bit line;   a second reference cell connected to said second bit line;   a potential line that supplies said reference potential to said first and second reference cells; and   a dummy cell provided in addition to said first and second reference cells and said first and second memory cells;   said dummy cell comprising a coupling capacitor whose one end is electrically connected directly to said potential line.   
     
     
         2 . The semiconductor memory device as defined in  claim 1 , wherein said first reference cell includes a first capacitor and a first transistor having its source or drain connected to said potential line and the other connected to an end of said first capacitor, and said second reference cell includes a second capacitor and a second transistor having its source or drain connected to said potential line and the other connected to an end of said second capacitor. 
     
     
         3 . The semiconductor memory device as defined in  claim 1 , wherein
 said first memory cell includes a first memory capacitor and a third transistor having its source or drain connected to said first bit line and the other connected to an end of said third capacitor, and said second memory cell includes a second memory capacitor and a fourth transistor having its source or drain connected to said second bit line and the other connected to an end of said fourth capacitor.   
     
     
         4 . The semiconductor memory device as defined in  claim 1 , wherein the other end of said coupling capacitor is connected to a fixed potential. 
     
     
         5 . The semiconductor memory device as defined in  claim 1 , wherein the other ends of said first to fourth capacitors are connected to a fixed potential. 
     
     
         6 . The semiconductor memory device as defined in  claim 4 , wherein said fixed potential is a half of a power supply voltage. 
     
     
         7 . The semiconductor memory device as defined in  claim 1 , wherein said dummy cell is disposed on an outer peripheral part of a cell array that includes said memory cell and said reference cell. 
     
     
         8 . The semiconductor memory device as defined in  claim 1  further comprising a logic circuit on the same substrate as a logic-embedded semiconductor memory device. 
     
     
         9 . A semiconductor memory device comprising:
 a comparing unit that compares a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell;   first and second bit lines connected to inputs of said comparing unit;   a first memory cell connected to said first bit line;   a second memory cell connected to said second bit line;   a first reference cell acting as said reference cell;   a second reference cell acting as another reference cell;   a potential line that supplies said reference potential to said first and second reference cells; and   a dummy cell comprising a coupling capacitor that stabilizes potential of said potential line.   
     
     
         10 . The semiconductor memory device as defined in  claim 9 , wherein another one of said dummy cell is provided in association with the second reference cell. 
     
     
         11 . A process for reading data of a memory cell comprising:
 providing a semiconductor memory device comprising:   first and second bit lines connected to a comparing unit;   a first memory cell connected to said first bit line;   a second memory cell connected to said second bit line;   a first reference cell connected to said first bit line;   a second reference cell connected to said second bit line;   a potential line that supplies said reference potential to said first and second reference cells;   a dummy cell comprising a coupling capacitor;   comparing potential of a memory cell with a reference potential of a reference cell;   wherein a potential of said coupling capacitor is directly supplied to said reference potential.   
     
     
         12 . The process as defined in  claim 11 , wherein said comparing of potential is carried out by comparing a potential of the second bit line with a reference potential of the first bit line supplied by the first reference cell which is stabilized by the dummy cell.