Semiconductor device and a method of manufacturing the same

Abstract

To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n + type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n − type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.

1 . A semiconductor device including a MISFET, comprising:
 a semiconductor substrate having a front surface and a rear surface opposite to the front surface;   a semiconductor layer formed over the front surface of the semiconductor substrate;   a gate insulating film of the MISFET formed over the semiconductor layer;   a gate electrode of the MISFET formed over the gate insulating film;   a first impurity region formed in the semiconductor layer and constituting a drain region of the MISFET or a source region of the MISFET;   a second impurity region formed in the semiconductor layer and constituting a drain region of the MISFET or a source region of the MISFET; and   a rear electrode formed on the rear surface of the semiconductor substrate,   wherein a groove is formed in the semiconductor layer and the semiconductor substrate,   wherein a conductive film is embedded into the groove,   wherein the first impurity region is electrically connected with the rear electrode via the conductive film,   wherein, in a plane view, a shape of the gate electrode is longer in a first direction than in a second direction which is substantially perpendicular to the first direction, and   wherein, in the plane view, a shape of the groove is longer in the first direction than in the second direction.   
     
     
         2 . A semiconductor device according to the  claim 1 , further comprising:
 an interlayer insulating film formed over the semiconductor layer, the conductive film and the MISFET;   a first plug formed in the interlayer insulating film and connected to the conductive film;   a second plug formed in the interlayer insulating film and connected to the first impurity region; and   a wiring formed over the interlayer insulating film and connected to the first and second plugs.   
     
     
         3 . A semiconductor device according to the  claim 2 ,
 wherein a plurality of the first plugs are formed in the interlayer insulating film and are connected to the conductive film.   
     
     
         4 . A semiconductor device according to the  claim 3 ,
 wherein, in the plane view, a shape of each the first plugs is longer in the second direction than in the first direction.   
     
     
         5 . A semiconductor device according to the  claim 4 ,
 wherein, in the plane view, a shape of the second plugs is longer in the first direction than in the second direction.   
     
     
         6 . A semiconductor device according to the  claim 3 ,
 wherein, in the plane view, a shape of the second plugs is longer in the first direction than in the second direction.   
     
     
         7 . A semiconductor device according to the  claim 1 ,
 wherein the conductive film includes a polysilicon film.   
     
     
         8 . A semiconductor device according to the  claim 1 ,
 wherein the conductive film includes a metal film.   
     
     
         9 . A semiconductor device according to the  claim 1 ,
 wherein the MISFET is configured to be used for a power amplifier circuit.   
     
     
         10 . A semiconductor device according to the  claim 1 , further comprising a plurality of the MISFETs,
 wherein, in the second direction, first and second MISFETs are abutted to each other in the second direction, and   wherein, in the second direction, the conductive film is arranged between the first impurity region of the first MISFET and the first impurity region of the second MISFET.   
     
     
         11 . A semiconductor device including a MISFET, comprising:
 a semiconductor substrate structure having a front surface and a rear surface opposite to the front surface;   a gate insulating film of the MISFET formed over the front surface of the semiconductor substrate structure;   a gate electrode of the MISFET formed over the gate insulating film;   a first impurity region formed in the semiconductor substrate structure and constituting a drain region of the MISFET or a source region of the MISFET;   a second impurity region formed in the semiconductor substrate structure and constituting a drain region of the MISFET or a source region of the MISFET; and   a rear electrode formed on the rear surface of the semiconductor substrate structure,   wherein a groove is formed in the semiconductor substrate structure,   wherein a conductive film is embedded into the groove,   wherein the first impurity region is electrically connected with the rear electrode via the conductive film,   wherein, in a plane view, a shape of the gate electrode is longer in a first direction than in a second direction which is substantially perpendicular to the first direction, and   wherein, in the plane view, a shape of the groove is longer in the first direction than in the second direction.   
     
     
         12 . A semiconductor device according to the  claim 11 , further comprising:
 an interlayer insulating film formed over the semiconductor substrate structure, the conductive film and the MISFET;   a first plug formed in the interlayer insulating film and connected to the conductive film;   a second plug formed in the interlayer insulating film and connected to the first impurity region; and   a wiring formed over the interlayer insulating film and connected to the first and second plugs.   
     
     
         13 . A semiconductor device according to the  claim 12 ,
 wherein a plurality of the first plugs are formed in the interlayer insulating film and are connected to the conductive film.   
     
     
         14 . A semiconductor device according to the  claim 13 ,
 wherein, in the plane view, a shape of each the first plugs is longer in the second direction than in the first direction.   
     
     
         15 . A semiconductor device according to the  claim 14 ,
 wherein, in the plane view, a shape of the second plugs is longer in the first direction than in the second direction.   
     
     
         16 . A semiconductor device according to the  claim 13 ,
 wherein, in the plane view, a shape of the second plugs is longer in the first direction than in the second direction.   
     
     
         17 . A semiconductor device according to the  claim 11 ,
 wherein the conductive film includes a polysilicon film.   
     
     
         18 . A semiconductor device according to the  claim 11 ,
 wherein the conductive film includes a metal film.   
     
     
         19 . A semiconductor device according to the  claim 11 ,
 wherein the MISFET is configured to be used for a power amplifier circuit.   
     
     
         20 . A semiconductor device according to the  claim 11 , further comprising a plurality of the MISFETs,
 wherein, in the second direction, first and second MISFETs are abutted to each other in the second direction, and   wherein, in the second direction, the conductive film is arranged between the first impurity region of the first MISFET and the first impurity region of the second MISFET.