Hierarchical configurations in error-correcting computer systems

Abstract

When errors arise in a computing system that has plural modules, this invention corrects those errors. In the first instance, the invention excludes the computing system itself, but receives error messages from the plural modules of that system—along plural receiving connections, respectively. Plural sending connections return corrective responses to plural modules of that system, respectively. In a second instance, the invention further incorporates that system. The invention is hierarchical: plural levels or tiers of apparatus and function are present—a first (typically uppermost) one directly serving that system as described above, and others (lower) that analogously serve the first tier of the invention—and than also the subsequent tiers, in a cascading or nested fashion, down to preferably a bottom-level tier supporting all the upper ones. Each level preferably controls power interruption and restoration to higher levels. Ideally the hierarchy is in the form of a “system on chip”.

1 . Apparatus for correcting errors, said errors being in a computing system that has plural modules, said modules having a structural computing-module hierarchy; and said apparatus comprising:
 an error-correcting system having a structural error-correcting hierarchy that is based upon and generally parallels the structural computing-module hierarchy;   at least two receiving connections, for reception by the hierarchical error-correcting system of error-message data, as distinguished from mere electrical return, from hierarchically corresponding plural modules of the computing system, respectively; and   at least two sending connections, for return by the hierarchical error-correcting system of corrective-response data, as distinguished from mere electrical return, hierarchically corresponding plural modules of the computing system, respectively.   
     
     
         2 . (canceled) 
     
     
         3 . The apparatus of  claim 1 ; wherein:
 the hierarchical error-correcting system comprises at least two first-level read-only modules, each first-level read-only module holding:
 a listing of error messages which respective modules of the computing system can send via one of the at-least-two data-receiving connections, and 
 a listing of respective corrective responses which respective modules of the computing system can receive via one of the at-least-two data-sending connections; and 
   each first-level read-only module comprises preprogrammed means for responding to receipt of any of the listed error messages from its respective module or modules by returning a respective corrective response.   
     
     
         4 . The apparatus of  claim 3 :
 in further combination with said computing system;   wherein power connections in the computing system are hardwired from the error-correcting system directly; and   wherein none of the receiving connections, and none of the sending connections, passes via the Internet.   
     
     
         5 . The apparatus of  claim 3 ; wherein the hierarchical system further comprises:
 at least one second-level read-only module having:
 at least two receiving connections for receiving error-message data messages from said at least two first-level read-only modules, respectively, and 
 at least two sending connections for returning corrective-response data to said at least two first-level read-only modules, respectively. 
   
     
     
         6 - 8 . (canceled) 
     
     
         9 . The apparatus of  claim 5 , further comprising:
 one or more read-only modules at additional levels having connections for receiving error-message data or returning corrective-response data and   at least one hypothalamus having preprogrammed means for controlling interruption and restoration of power to at least one read-only module of the hierarchy; and   wherein each of said corrective-response data is physically self implementing without human intervention;   in further combination with said computing system;   wherein power connections in the computing system are hardwired with the error-correcting system directly; and   wherein none of the receiving connections, and none of the sending connections, passes via the Internet.   
     
     
         10 - 20 . (canceled) 
     
     
         21 . The apparatus of  claim 1 , wherein:
 at least the error-correcting system is in the form of a System on Chip (SoC).   
     
     
         22 . The apparatus of  claim 1 , wherein:
 the apparatus is all hardware and firmware, having no software.   
     
     
         23 . The apparatus of  claim 1 , wherein:
 the apparatus does not interfere with operation of the computing system except when the computing system sends an error message to the apparatus.   
     
     
         24 . The apparatus of  claim 1 , wherein:
 the apparatus itself is fault-tolerant.   
     
     
         25 . Apparatus for correcting errors, said errors being in a computing system that has plural modules, said modules having a structural computing-module hierarchy; and said apparatus comprising:
 an error-correcting system having a structural error-correcting hierarchy that is based upon and generally parallels the structural computing-module hierarchy;   wherein the apparatus itself is fault-tolerant.   
     
     
         26 . The apparatus of  claim 25 , wherein:
 the apparatus does not interfere with operation of the computing system except when the computing system sends an error message to the apparatus.   
     
     
         27 . The apparatus of  claim 26 , wherein:
 the apparatus is all hardware and firmware, having no software.   
     
     
         28 . Apparatus for correcting errors, said errors being in a computing system that has plural modules, said modules having a structural computing-module hierarchy; and said apparatus comprising:
 an error-correcting system having a structural error-correcting hierarchy that is based upon and generally parallels the structural computing-module hierarchy;   wherein the apparatus does not interfere with operation of the computing system except when the computing system sends an error message to the apparatus.